APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 19

• Manufacturer Part Number: APA075-BGB
• Description: ProASIC Flash Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

Timing Control and
Characteristics
ProASIC
ProASIC
clock conditioning capabilities. Each member of the
ProASIC
blocks which perform the following functions:
Each PLL has the following key features:
Note: Jitter(ps) = Jitter(%)* period
For Example:
Physical Implementation
Each side of the chip contains a clock conditioning circuit
based on a 180 MHz PLL block
14). Two global multiplexed lines extend along each side
of the chip to provide bidirectional access to the PLL on
that side (neither MUX can be connected to the opposite
side's PLL). Each global line has optional LVPECL input
pads (described below). The global lines may be driven
by either the LVPECL global input pad or the outputs
from the PLL block, or both. Each global line can be
driven by a different output from the PLL. Unused global
pins can be configured as regular I/Os or left
unconnected. They default to an input with pull-up. The
two signals available to drive the global networks are as
Jitter in picoseconds at 100 MHz = 0.01 * (1/100E6) = 100 ps
• Clock Phase Adjustment via Programmable Delay
• Clock Skew Minimization
• Clock Frequency Synthesis
• Input Frequency Range (f
• Feedback Frequency Range (f
• Output Frequency Range (f
• Output Phase Shift = 0 ° and 180 °
• Output Duty Cycle = 50%
• Low Output Jitter (max at 25°C)
• Low Power Consumption – 6.9 mW (max – analog
• Maximum Acquisition
1. This mode is available through the delay feature of the Global MUX driver.
(250 ps steps from –7 ns to +8 ns)
– f
– 10 MHz < f
– f
supply) + 7.0μW/MHz (max – digital supply)
Time
PLUS
PLUS
VCO
VCO
PLUS
devices provide designers with very flexible
family contains two phase-locked loop (PLL)
<10 MHz. Jitter ±1% or better
> 60 MHz. Jitter ±1% or better
Clock Management System
VCO
< 60 MHz. Jitter ±2% or better
= 80 µs for f
= 30 µs for f
IN
(Figure 1-14 on page 1-
) = 1.5 to 180 MHz
OUT
VCO
) = 8 to 180 MHz
) = 24 to 180 MHz
VCO
VCO
> 40 MHz
< 40 MHz
v5.7
follows
15, and
Global A (secondary clock)
Global B
Functional Description
Each PLL block contains four programmable dividers as
shown in
frequency scaling of the input clock signal as follows:
The implementations shown in EQ2 and EQ3 enable the
user to define a wide range of frequency multiplier and
divisors.
• Output from Global MUX A
• Conditioned version of PLL output (f
• Divided version of either of the above
• Further delayed version of either of the above
• Output from Global MUX B
• Delayed or advanced version of f
• Divided version of either of the above
• Further delayed version of either of the above
• The n divider divides the input clock by integer
• The m divider in the feedback path allows
• The two dividers together can implement any
• The output frequency of the PLL core is given by
• The third and fourth dividers (u and v) permit the
f
f
f
OUT
GLB
GLA
or advanced
(0.25 ns, 0.50 ns, or 4.00 ns delay)
(0.25 ns, 0.50 ns, or 4.00 ns delay)
factors from 1 to 32.
multiplication of the input clock by integer factors
ranging from 1 to 64.
combination
resulting in a clock frequency between 24 and 180
MHz exiting the PLL core. This clock has a fixed
50% duty cycle.
the formula
frequency):
signals applied to the global network to each be
further divided by integer factors ranging from 1
to 4.
Table 1-8 on page
(Figure 1-15 on page
= m/(n*u)
= m/(n*v)
= f
REF
Figure 1-14 on page
* m/n
EQ 1-1
of
ProASIC
1-16):
multiplication
(f
REF
1-15,
PLUS
is the reference clock
Table 1-7 on page 1-
1-14. These allow
Flash Family FPGAs
OUT
1
2
OUT
and
) – delayed
division
EQ 1-1
EQ 1-2
EQ 1-3
1-13