DS80C320-ECD DALLAS [Dallas Semiconductor], DS80C320-ECD Datasheet - Page 134

• Manufacturer Part Number: DS80C320-ECD
• Description: High-Speed Microcontroller User Guide
• Manufacturer: DALLAS [Dallas Semiconductor]

WATCHDOG TIMER
The Watchdog Timer is a user programmable clock counter that can serve as a time-base generator, an
event timer, or a system supervisor. As can be seen in the diagram of Figure 11-8, the timer is driven by
the main system clock that is supplied to a series of dividers. The divider output is selectable, and
determines the interval between time-outs. When the time-out is reached, an interrupt flag will be set,
and if enabled, a reset will occur. The interrupt flag will cause an interrupt to occur if its individual
enable bit is set and the global interrupt enable is set. The reset and interrupt are completely discrete
functions that may be acknowledged or ignored, together or separately for various applications.
WATCHDOG TIMER Figure 11-8
The Watchdog Timer Reset function works as follows. After initializing the correct time-out interval
(discussed below), software first restarts the Watchdog using RWT(WDCON.0) and then enables the
reset mode by setting the Enable Watchdog Timer Reset (EWT = WDCON.1) bit. At any time prior to
reaching its user selected terminal value, software can set the Reset Watchdog Timer (RWT =
WDCON.0) bit. If RWT is set before the time-out is reached, the timer will start over. If the time-out is
reached without RWT being set, the Watchdog will reset the CPU. Hardware will automatically clear
RWT after software sets it.
WDCON.2) will automatically be set to indicate the cause of the reset, however software must clear this
bit manually.
XTAL1
XTAL2
CLOCK DIVIDE CONTROL
CD1
No PMR register
0
1
1
DIVIDE BY
1/16/256
WD1 (CKCON.7)
WD0 (CKCON.6)
CD0
X
0
1
DIVISOR
1
1
16
256
When the reset occurs, the Watchdog Timer Reset Flag (WTRF =
DIVIDE BY
2
17
(Enable Watchdog Timer
2
DIVIDE BY
17
134 of 175
2
EWT (WDCON.1)
3
SELECTOR
(WDCON.3)
512 CLOCK
TIME-OUT
DELAY
(Enable Watchdog
WDIF
2
EWDI (EIE.4)
DIVIDE BY
20
2
2
3
23
High-Speed Microcontroller User’s Guide
2
26
DIVIDE BY
TIME-OUT
2
3
RWT (WDCON.0
(Reset Watchdog)
(WDCON.2)
WTRF
WATCHDOG
INTERRUPT
RESET