DS80C320-ECD DALLAS [Dallas Semiconductor], DS80C320-ECD Datasheet - Page 45

• Manufacturer Part Number: DS80C320-ECD
• Description: High-Speed Microcontroller User Guide
• Manufacturer: DALLAS [Dallas Semiconductor]

Time Access Register (TA)
Time 2 Control (T2CON)
SFR C7h
TA.7-0
Bits 7-0
SFR C8h
TF2
Bit 7
EXF2
Bit 6
RCLK
Bit 5
CP/
1
1
0
0
0
RL2
W=Unrestricted Write, -n=Value after Reset
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
RW-0
TA.7
W-1
TF2
7
7
EXEN2
X
0
1
0
1
Timed Access. Correctly accessing this register permits modification of timed
access protected bits. Write AAh to this register first, followed within 3 cycles
by writing 55h. Timed access protected bits can then be modified for a period of
3 cycles measured from the writing of the 55h.
Timer 2 Overflow Flag. This flag will be set when Timer 2 overflows from
FFFFh or the count equal to the capture register in down count mode. It must be
cleared by software. TF2 will only be set if RCLK and TCLK are both cleared to
0.
Timer 2 External Flag. A negative transition on the T2EX pin (P1.1) or timer 2
underflow/overflow will cause this flag to set based on the CP/
EXEN2 (T2CON.3), and DCEN (T2MOD.0) bits. If set by a negative transition,
this flag must be cleared to 0 by software. Setting this bit in software or
detection of a negative transition on the T2EX pin will force a timer interrupt if
enabled.
Receive Clock Flag. This bit determines the serial port 0 timebase when
receiving data in serial modes 1 or 3.
0 = Timer 1 overflow is used to determine receiver baud rate for serial port 0.
1 = Timer 2 overflow is used to determine receiver baud rate for serial port 0.
Setting this bit will force timer 2 into baud rate generation mode. The timer
will operate from a divide by 2 of the external clock.
EXF2
RW-0
TA.6
W-1
6
6
DCEN
RCLK
RW-0
TA.5
W-1
X
X
0
0
1
5
5
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RESULT
Negative transitions on P1.1 will not affect this bit.
Negative transitions on P1.1 will set this bit.
Negative transitions on P1.1 will not affect this bit.
Negative transitions on P1.1 will set this bit.
Bit toggles whenever timer 2 underflows/overflows
and can be used as a 17
mode, EXF2 will not cause an interrupt.
TCLK
RW-0
TA.4
W-1
4
4
EXEN2
RW-0
TA.3
W-1
3
3
High-Speed Microcontroller User’s Guide
th
RW-0
TA.2
W-1
TR2
bit of resolution. In this
2
2
RW-0
C/
TA.1
W-1
RL2
1
1
T2
(T2CON.0),
CP/RL2
RW-0
TA.0
W-1
0
0