DS80C320-ECD DALLAS [Dallas Semiconductor], DS80C320-ECD Datasheet - Page 42

• Manufacturer Part Number: DS80C320-ECD
• Description: High-Speed Microcontroller User Guide
• Manufacturer: DALLAS [Dallas Semiconductor]

Power Management Register (PMR)
SFR C4h
CD1, CD0
Bits 7-6
SWB
Bit 5
Bit 4
XTOFF
Bit 3
CD1
0
0
1
1
CD0
0
1
0
1
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset, *=See description
CD1
CYCLES
MACH.
CYCLE
7
OSC
PER
1024
64
4
Clock Divide Control 1-0. These bits select the number of crystal oscillator
clocks required to generate one machine cycle.
requires a transition through the divide by 4 mode (CD1, CD0=01).
example, to go from 64 to 1024 clocks per cycle the device must first go from 64
to 4 clocks per cycle, and then from 4 to 1024 clocks per cycle. Attempts to
perform an invalid transition will be ignored. The setting of these bits will effect
the timers and serial ports as shown below.
Switchback Enable. This bit allows an enabled external interrupt or serial port
activity to force the Clock Divide Control bits to the divide by 4 state (01).
Upon internal acknowledgement of an external interrupt, the device will switch
modes at the start of the jump to the interrupt service routine. Note that this
means that an external interrupt must actually be recognized (i.e., be enabled and
not masked by higher priority interrupts) for the switchback to occur. For serial
port reception, the switch occurs at the start of the instructions following the
falling edge of the start bit.
Reserved. When modifying the PMR register, software must write a 0 to this
bit. Read data will be indeterminate.
Crystal Oscillator Disable. This bit disables the CPU crystal oscillator. It can
only be set to 1 while running the ring oscillator (XT/
restarts the crystal amplifier, reset the crystal warm-up counter, and after 65,536
external crystal cycles the XTUP bit will be set.
0 = Crystal oscillator is enabled.
1 = Crystal oscillator is disabled.
RW-1
CD0
TxM=0
6
3072
192
PER TIMER 2
OSC CYCLES
12
CLK, BAUD
RATE GEN.
TxM=1
RW-0
SWB
1024
64
5
4
T2M=0
42 of 175
OSC CYCLES
512
PER SERIAL
32
PORT CLK,
2
MODE 0
4
-
RESERVED
T2M=1
512
32
2
XTOFF
RW*-0
3
SM2=0
PER TIMER 2
3072
OSC CYCLES
194
CLK, BAUD
RATE GEN.
12
High-Speed Microcontroller User’s Guide
ALEOFF
RW-0
SM2=1
2
1024
Switching between modes
64
4
RG
=0). Clearing this bit
SDMO=0
SERIAL PORT CLK,
DME1
RW-0
OSC CYCLES PER
16384
1024
1
64
MODE 2
SMOD=1
DME0
RW-0
8192
512
32
0
For