DS80C320-ECD DALLAS [Dallas Semiconductor], DS80C320-ECD Datasheet - Page 137
DS80C320-ECD
Manufacturer Part Number
DS80C320-ECD
Description
High-Speed Microcontroller User Guide
Manufacturer
DALLAS [Dallas Semiconductor]
Datasheet
1.DS80C320-ECD.pdf
(175 pages)
- Current page: 137 of 175
- Download datasheet (2Mb)
WDCON.0
Read/write access:
CKCON.7
CKCON.6
The default Watchdog time-out is the shortest one (WD1=WD0=0). Software can change this value
easily, so this should cause no inconvenience. However, the EWT, WDIF, and RWT bits are protected
under the Timed Access procedure. This prevents software from accidentally enabling or disabling the
Watchdog. Most importantly, it prevents errant code from accidentally clearing and restarting the
Watchdog. More details are discussed in the section on Timed Access.
CLOCK CONTROL
RWT - Reset Watchdog Timer. This bit serves as the strobe for the
Watchdog function. During the time-out period, software must set
the RWT bit if the Watchdog is enabled. Failing to set the RWT
will cause a reset when the time-out has elapsed. There is no need
to set the RWT bit to a 0 because it is self-clearing.
All bits have unrestricted read access. POR, EWT, WDIF, and RWT require a
Timed Access write. The remaining bits have unrestricted write access.
CKCON; 8Eh
WD1 - Watchdog Timer mode select bit 1. See table below for
operation.
WD0 - Watchdog Timer mode select bit 0. See table below for
operation. The WD select bits determine the time-out period of the
Watchdog Timer. The timer divides the crystal frequency by a
programmable value as shown below.
expressed in number of clock (crystal) cycles. Note that the reset
time-out is 512 clocks longer than the interrupt, regardless of
whether the interrupt is enabled.
WD1
0
0
1
1
WD0
0
1
0
1
137 of 175
Interrupt
Divider
2
2
2
2
17
20
23
26
High-Speed Microcontroller User’s Guide
Reset
Divider
2
2
2
2
17
20
23
26
+ 512
+ 512
+ 512
+ 512
The divider value is
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