ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 12

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF534/ADSP-BF536/ADSP-BF537
PORTS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
group the many peripheral signals to four ports—Port F, Port G,
Port H, and Port J. Most of the associated pins are shared by
multiple signals. The ports function as multiplexer controls.
Eight of the pins (Port F7–0) offer high source/high sink current
capabilities.
General-Purpose I/O (GPIO)
The processors have 48 bidirectional, general-purpose I/O
(GPIO) pins allocated across three separate GPIO modules—
PORTFIO, PORTGIO, and PORTHIO, associated with Port F,
Port G, and Port H, respectively. Port J does not provide GPIO
functionality. Each GPIO-capable pin shares functionality with
other processor peripherals via a multiplexing scheme; however,
the GPIO functionality is the default state of the device upon
power-up. Neither GPIO output or input drivers are active by
default. Each general-purpose port pin can be individually con-
trolled by manipulation of the port control, status, and interrupt
registers:
• Programmable Rx address filters, including a 64-bit
• Advanced power management supporting unattended
• System wakeup from sleep operating mode upon magic
• Support for 802.3Q tagged VLAN frames.
• Programmable MDC clock rate and preamble suppression.
• In RMII operation, 7 unused pins may be configured as
• GPIO direction control register – Specifies the direction of
• GPIO control and status registers – The processors employ
• GPIO interrupt mask registers – The two GPIO interrupt
address hash table for multicast and/or unicast frames, and
programmable filter modes for broadcast, multicast, uni-
cast, control, and damaged frames.
transfer of Rx and Tx frames and status to/from external
memory via DMA during low-power sleep mode.
packet or any of four user-definable wakeup frame filters.
GPIO pins for other purposes.
each individual GPIO pin as input or output.
a “write one to modify” mechanism that allows any combi-
nation of individual GPIO pins to be modified in a single
instruction, without affecting the level of any other GPIO
pins. Four control registers are provided. One register is
written in order to set pin values, one register is written in
order to clear pin values, one register is written in order to
toggle pin values, and one register is written in order to
specify a pin value. Reading the GPIO status register allows
software to interrogate the sense of the pins.
mask registers allow each individual GPIO pin to function
as an interrupt to the processor. Similar to the two GPIO
control registers that are used to set and clear individual
pin values, one GPIO interrupt mask register sets bits to
enable interrupt function, and the other GPIO interrupt
mask register clears bits to disable interrupt function.
Rev. B | Page 12 of 68 | July 2006
PARALLEL PERIPHERAL INTERFACE (PPI)
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-
vide a parallel peripheral interface (PPI) that can connect
directly to parallel A/D and D/A converters, ITU-R-601/656
video encoders and decoders, and other general-purpose
peripherals. The PPI consists of a dedicated input clock pin, up
to 3 frame synchronization pins, and up to 16 data pins.
In ITU-R-656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information
is supported.
Three distinct ITU-R-656 modes are supported:
Though not explicitly supported, ITU-R-656 output functional-
ity can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor’s 2-D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:
• GPIO interrupt sensitivity registers – The two GPIO inter-
• Active video only mode – The PPI does not read in any
• Vertical blanking only mode – The PPI only transfers verti-
• Entire field mode – The entire incoming bitstream is read
• Data receive with internally generated frame syncs
• Data receive with externally generated frame syncs
• Data transmit with internally generated frame syncs
• Data transmit with externally generated frame syncs
GPIO pins defined as inputs can be configured to generate
hardware interrupts, while output pins can be triggered by
software interrupts.
rupt sensitivity registers specify whether individual pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
data between the End of Active Video (EAV) and Start of
Active Video (SAV) preamble symbols, or any data present
during the vertical blanking intervals. In this mode, the
control byte sequences are not stored to memory; they are
filtered by the PPI.
cal blanking interval (VBI) data, as well as horizontal
blanking information and control byte sequences on
VBI lines.
in through the PPI. This includes active video, control pre-
amble sequences, and ancillary data that may be embedded
in horizontal and vertical blanking intervals.