ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 7

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Conceptually, interrupts from the peripherals enter into the
SIC, and are then routed directly into the general-purpose inter-
rupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the Blackfin processor.
Table 2
in the event vector table (EVT), and lists their priorities.
Table 2. Core Event Controller (CEC)
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout-
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processor provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writ-
ing the appropriate values into the interrupt assignment
registers (IAR).
default mappings into the CEC.
Priority
(0 Is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
describes the inputs to the CEC, identifies their names
Table 3
Event Class
Emulation/Test Control
Reset
Nonmaskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General-Purpose Interrupt 7
General-Purpose Interrupt 8
General-Purpose Interrupt 9
General-Purpose Interrupt 10
General-Purpose Interrupt 11
General-Purpose Interrupt 12
General-Purpose Interrupt 13
General-Purpose Interrupt 14
General-Purpose Interrupt 15
describes the inputs into the SIC and the
EVT Entry
EMU
RST
NMI
EVX
—
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
Rev. B | Page 7 of 68 | July 2006
Table 3. System Interrupt Controller (SIC)
ADSP-BF534/ADSP-BF536/ADSP-BF537
Peripheral Interrupt Event
PLL Wakeup
DMA Error (generic)
DMAR0 Block Interrupt
DMAR1 Block Interrupt
DMAR0 Overflow Error
DMAR1 Overflow Error
CAN Error
Ethernet Error (ADSP-BF536 and
ADSP-BF537 only)
SPORT 0 Error
SPORT 1 Error
PPI Error
SPI Error
UART0 Error
UART1 Error
Real-Time Clock
DMA Channel 0 (PPI)
DMA Channel 3 (SPORT 0 Rx)
DMA Channel 4 (SPORT 0 Tx)
DMA Channel 5 (SPORT 1 Rx)
DMA Channel 6 (SPORT 1 Tx)
TWI
DMA Channel 7 (SPI)
DMA Channel 8 (UART0 Rx)
DMA Channel 9 (UART0 Tx)
DMA Channel 10 (UART1 Rx)
DMA Channel 11 (UART1 Tx)
CAN Rx
CAN Tx
DMA Channel 1 (Ethernet Rx,
ADSP-BF536 and ADSP-BF537 only)
Port H Interrupt A
DMA Channel 2 (Ethernet Tx,
ADSP-BF536 and ADSP-BF537 only)
Port H Interrupt B
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Timer 7
Port F, G Interrupt A
Port G Interrupt B
Default
Mapping
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG8
IVG9
IVG9
IVG9
IVG9
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
Peripheral
Interrupt ID
0
1
1
1
1
1
2
2
2
2
2
2
2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
17
18
18
19
20
21
22
23
24
25
26
27
28