ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 33

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Parallel Peripheral Interface Timing
Table 23
Figure 20 on Page 38
operations.
Table 23. Parallel Peripheral Interface Timing
1
Parameter
Timing Requirements
t
t
Timing Requirements—GP Input and Frame Capture Modes
t
t
t
t
Switching Characteristics—GP Output and Frame Capture Modes
t
t
t
t
PPI_CLK frequency cannot exceed f
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
PPI_FS1
PPI_FS2
PPI_DATA
PCLKW
PCLK
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
POLS = 1
POLS = 0
POLS = 1
POLS = 0
and
Figure 15 on Page
PPI_CLK Width
PPI_CLK Period
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
describe parallel peripheral interface
SCLK
33,
/2.
1
1
Figure 19 on Page
DATA
SAMPLING
EDGE
t
HOFSPE
Figure 15. PPI GP Rx Mode with Internal Frame Sync Timing
FRAME
SYNC
DRIVING
EDGE
t
DFSPE
Rev. B | Page 33 of 68 | July 2006
t
SDRPE
37, and
DATA
SAMPLING
EDGE
t
HDRPE
ADSP-BF534/ADSP-BF536/ADSP-BF537
Min
6.0
15.0
6.7
1.0
3.5
1.5
1.7
1.8
Max
8.0
8.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns