ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 44

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF534/ADSP-BF536/ADSP-BF537
Timer Cycle Timing
Table 31
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
Table 31. Timer Cycle Timing
1
2
Parameter
Timing Characteristics
t
t
t
t
Switching Characteristics
t
t
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
WL
WH
TIS
TIH
HTO
TOD
and
SCLK
Figure 26
TIME R O UTPUT
/2) MHz.
TIM E R INPUT
Timer Pulse Width Input Low (Measured In SCLK Cycles)
Timer Pulse Width Input High (Measured In SCLK Cycles)
Timer Input Setup Time Before CLKOUT Low
Timer Input Hold Time After CLKOUT Low
Timer Pulse Width Output (Measured In SCLK Cycles)
Timer Output Update Delay After CLKOUT High
CLKO UT
describe timer expired operations. The
Rev. B | Page 44 of 68 | July 2006
t
T IS
Figure 26. Timer Cycle Timing
2
2
t
W H ,
t
t
W L
TIH
1
1
t
H T O
t
TO D
Min
1 t
1 t
5
–2
1 t
SCLK
SCLK
SCLK
Max
(2
6
32
–1) t
SCLK
Unit
ns
ns
ns
ns
ns
ns