ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 16

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF534/ADSP-BF536/ADSP-BF537
BOOTING MODES
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor has six
mechanisms (listed in
nal and external memory after a reset. A seventh mode is
provided to execute from external memory, bypassing the boot
sequence.
Table 8. Booting Modes
The BMODE pins of the reset configuration register, sampled
during power-on resets and software-initiated resets, imple-
ment the following modes:
BMODE2–0
000
001
010
011
100
101
110
111
• Execute from 16-bit external memory – Execution starts
• Boot from 8-bit and 16-bit external flash memory – The
• Boot from serial SPI memory (EEPROM or flash) – 8-, 16-,
• Boot from SPI host device – The Blackfin processor oper-
from address 0x2000 0000 with 16-bit packing. The boot
ROM is bypassed in this mode. All configuration settings
are set for the slowest device possible (3-cycle hold time;
15-cycle R/W access times; 4-cycle setup).
8-bit or 16-bit flash boot routine located in Boot ROM
memory space is set up using asynchronous memory bank
0. All configuration settings are set for the slowest device
possible (3-cycle hold time; 15-cycle R/W access times;
4-cycle setup). The Boot ROM evaluates the first byte of the
boot stream at address 0x2000 0000. If it is 0x40, 8-bit boot
is performed. A 0x60 byte assumes a 16-bit memory device
and performs 8-bit DMA. A 0x20 byte also assumes 16-bit
memory but performs 16-bit DMA.
or 24-bit addressable devices are supported as well as
AT45DB041, AT45DB081, AT45DB161, AT45DB321,
AT45DB642, and AT45DB1282 DataFlash
Atmel. The SPI uses the PF10/SPI SSEL1 output pin to
select a single SPI EEPROM/flash device, submits a read
command and successive address bytes (0x00) until a valid
8-, 16-, or 24-bit, or Atmel addressable device is detected,
and begins clocking data into the processor.
ates in SPI slave mode and is configured to receive the bytes
of the .LDR file from an SPI host (master) agent. To hold
off the host device from transmitting while the boot ROM
is busy, the Blackfin processor asserts a GPIO pin, called
host wait (HWAIT), to signal the host device not to send
Description
Execute from 16-bit external memory (bypass
boot ROM)
Boot from 8-bit or 16-bit memory
(EPROM/flash)
Reserved
Boot from serial SPI memory (EEPROM/flash)
Boot from SPI host (slave mode)
Boot from serial TWI memory (EEPROM/flash)
Boot from TWI host (slave mode)
Boot from UART host (slave mode)
Table
8) for automatically loading inter-
®
devices from
Rev. B | Page 16 of 68 | July 2006
For each of the boot modes, a 10-byte header is first brought in
from an external device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the start of L1 instruction SRAM.
In addition, Bit 4 of the reset configuration register can be set by
application code to bypass the normal boot sequence during a
software reset. For this case, the processor jumps directly to the
beginning of L1 instruction memory.
To augment the boot modes, a secondary software loader can be
added to provide additional booting mechanisms. This second-
ary loader could provide the capability to boot from flash,
variable baud rate, and other sources. In all boot modes except
bypass, program execution starts from on-chip L1 memory
address 0xFFA0 0000.
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the
• Boot from UART – Using an autobaud handshake
• Boot from serial TWI memory (EEPROM/flash) – The
• Boot from TWI host – The TWI host agent selects the slave
any more bytes until the flag is deasserted. The flag is cho-
sen by the user and this information is transferred to the
Blackfin processor via bits 10:5 of the FLAG header.
sequence, a boot-stream-formatted program is downloaded
by the host. The host agent selects a baud rate within the
UART’s clocking capabilities. When performing the auto-
baud, the UART expects an “@” (boot stream) character
(8 bits data, 1 start bit, 1 stop bit, no parity bit) on the RXD
pin to determine the bit rate. It then replies with an
acknowledgement that is composed of 4 bytes: 0xBF, the
value of UART_DLL, the value of UART_DLH, and 0x00.
The host can then download the boot stream. When the
processor needs to hold off the host, it deasserts CTS.
Therefore, the host must monitor this signal.
Blackfin processor operates in master mode and selects the
TWI slave with the unique ID 0xA0. It submits successive
read commands to the memory device starting at two byte
internal address 0x0000 and begins clocking data into the
processor. The TWI memory device should comply with
Philips I
bility to auto-increment its internal address counter such
that the contents of the memory device can be read
sequentially.
with the unique ID 0x5F. The processor replies with an
acknowledgement and the host can then download the
boot stream. The TWI host agent should comply with
Philips I
plexer can be used to select one processor at a time when
booting multiple processors from a single TWI.
2
2
C Bus Specification version 2.1 and have the capa-
C Bus Specification version 2.1. An I
2
C multi-