ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 47

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

10/100 Ethernet MAC Controller Timing
Table 34
describe the 10/100 Ethernet MAC controller operations. This
feature is only available on the ADSP-BF536 and ADSP-BF537
processors. For more information, see
Table 34. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
1
Table 35. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
1
Table 36. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
1
Table 37. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
1
Parameter
t
t
t
t
MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
Parameter
t
t
t
t
MII outputs synchronous to ETxCLK are ETxD3–0.
Parameter
t
t
t
t
RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
Parameter
t
t
RMII outputs synchronous to RMII REF_CLK are ETxD1–0.
ERXCLKF
ERXCLKW
ERXCLKIS
ERXCLKIH
ETF
ETXCLKW
ETXCLKOV
ETXCLKOH
EREFCLKF
EREFCLKW
EREFCLKIS
EREFCLKIH
EREFCLKOV
EREFCLKOH
through
1
1
1
1
ERxCLK Frequency (f
ERxCLK Width (t
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)
ETxCLK Frequency (f
ETxCLK Width (t
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)
ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold)
REF_CLK Frequency (f
EREF_CLK Width (t
Rx Input Valid to RMII REF_CLK Rising Edge (Data In Setup)
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In Hold)
Table 39
RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid)
RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold)
and
Figure 29
ETxCLK
ERxCLK
EREFCLK
SCLK
SCLK
= ETxCLK Period)
= ERxCLK Period)
SCLK
Table 1 on Page
= SCLK Frequency)
= SCLK Frequency)
= EREFCLK Period)
through
= SCLK Frequency)
Figure 34
Rev. B | Page 47 of 68 | July 2006
3.
ADSP-BF534/ADSP-BF536/ADSP-BF537
Min
None
t
7.5
7.5
Min
None
t
0
Min
None
t
4
2
ERxCLK
ETxCLK
EREFCLK
35%
35%
35%
Min
2
Max
25 MHz + 1%
f
t
Max
25 MHz + 1%
f
t
20
Max
50 MHz + 1%
2 f
t
SCLK
ERxCLK
SCLK
ETxCLK
EREFCLK
SCLK
+ 1%
+ 1%
65%
65%
+ 1%
65%
Max
7.5
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns