ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 9

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

In addition to the dedicated peripheral DMA channels, there are
two memory DMA channels provided for transfers between the
various memories of the processor system. This enables trans-
fers of blocks of data between any of the memories—including
external SDRAM, ROM, SRAM, and flash memory—with mini-
mal processor intervention. Memory DMA transfers can be
controlled by a very flexible descriptor-based methodology or
by a standard register-based autobuffer mechanism.
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors also
have an external DMA controller capability via dual external
DMA request pins when used in conjunction with the external
bus interface unit (EBIU). This functionality can be used when a
high speed interface is required for external FIFOs and high
bandwidth communications peripherals such as USB 2.0. It
allows control of the number of data transfers for memDMA.
The number of transfers per edge is programmable. This feature
can be programmed to allow memDMA to have an increased
priority on the external bus relative to the core.
REAL-TIME CLOCK
The real-time clock (RTC) provides a robust set of digital watch
features, including current time, stopwatch, and alarm. The
RTC is clocked by a 32.768 kHz crystal external to the
processor. The RTC peripheral has dedicated power supply pins
so that it can remain powered up and clocked even when the
rest of the processor is in a low-power state. The RTC provides
several programmable interrupt options, including interrupt
per second, minute, hour, or day clock ticks, interrupt on pro-
grammable stopwatch countdown, or interrupt at a
programmed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60-second counter, a 60-minute counter, a
24-hour counter, and an 32,768-day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day, while the second alarm is for a day and time of
that day.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the processor
from sleep mode upon generation of any RTC wakeup event.
Additionally, an RTC wakeup event can wake up the processor
from deep sleep mode, and wake up the on-chip internal voltage
regulator from the hibernate operating mode.
Connect RTC pins RTXI and RTXO with external components
as shown in
WATCHDOG TIMER
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors
include a 32-bit timer that can be used to implement a software
watchdog function. A software watchdog can improve system
availability by forcing the processor to a known state through
generation of a hardware reset, nonmaskable interrupt (NMI),
Figure
4.
Rev. B | Page 9 of 68 | July 2006
or general-purpose interrupt, if the timer expires before being
reset by software. The programmer initializes the count value of
the timer, enables the appropriate interrupt, then enables the
timer. Thereafter, the software must reload the counter before it
counts to zero from the programmed value. This protects the
system from remaining in an unknown state where software,
which would normally reset the timer, has stopped running due
to an external noise condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the processor peripherals. After a reset,
software can determine if the watchdog was the source of the
hardware reset by interrogating a status bit in the watchdog
timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of f
TIMERS
There are nine general-purpose programmable timer units in
the processor. Eight timers have an external pin that can be con-
figured either as a pulse width modulator (PWM) or timer
output, as an input to clock the timer, or as a mechanism for
measuring pulse widths and periods of external events. These
timers can be synchronized to an external clock input to the sev-
eral other associated PF pins, to an external clock input to the
PPI_CLK input pin, or to the internal SCLK.
The timer units can be used in conjunction with the two UARTs
and the CAN controller to measure the width of the pulses in
the data stream to provide a software auto-baud detect function
for the respective serial channels.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the eight general-purpose programmable timers,
a ninth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generating periodic interrupts in an operating system.
ADSP-BF534/ADSP-BF536/ADSP-BF537
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12pF LOAD (SURFACE MOUNT PACKAGE)
C1 = 22pF
C2 = 22pF
R1 = 10M
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3pF.
C1
RTXI
SCLK
Figure 4. External Components for RTC
.
R1
X1
C2
YSTAL SPECIFIED FOR X1.
RTXO