ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 14

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF534/ADSP-BF536/ADSP-BF537
Table 5. Power Domains
The dynamic power management feature allows both the pro-
cessor’s input voltage (V
dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in power dissipation, while reducing the voltage by
25% reduces power dissipation by more than 40%. Further,
these power savings are additive, in that if the clock frequency
and supply voltage are both reduced, the power savings can be
dramatic, as shown in the following equations.
The power savings factor is calculated as:
where the variables in the equations are:
The percent power savings is calculated as:
VOLTAGE REGULATION
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor pro-
vides an on-chip voltage regulator that can generate processor
core voltage levels (0.85 V to 1.2 V guaranteed from –5% to
+10%) from an external 2.25 V to 3.6 V supply.
the typical external components required to complete the power
management system. The regulator controls the internal logic
voltage levels and is programmable with the voltage regulator
control register (VR_CTL) in increments of 50 mV. To reduce
standby power consumption, the internal voltage regulator can
be programmed to remove power to the processor core while
keeping I/O power supplied. While in hibernate mode, V
can still be applied, eliminating the need for external buffers.
The voltage regulator can be activated from this power-down
state by asserting the RESET pin, which then initiates a boot
sequence. The regulator can also be disabled and bypassed at the
user’s discretion.
Power Domain
All internal logic, except RTC
RTC internal logic and crystal I/O
All other I/O
f
f
V
V
T
T
% power savings
CCLKNOM
CCLKRED
NOM
RED
DDINTNOM
DDINTRED
is the duration running at f
power savings factor
is the duration running at f
=
is the reduced core clock frequency
is the nominal core clock frequency
-------------------- -
f
f
is the reduced internal supply voltage
CCLKNOM
is the nominal internal supply voltage
CCLKRED
=
DDINT
⎛
⎝
1 power savings factor
------------------------- -
V
V
–
) and clock frequency (f
DDINTNOM
DDINTRED
CCLKRED
CCLKNOM
⎞
⎠
2
⎛
⎝
------------ -
T
T
NOM
RED
Figure 5
V
V
V
V
DDINT
DDRTC
DDEXT
DD
⎞
⎠
CCLK
Range
Rev. B | Page 14 of 68 | July 2006
100%
) to be
shows
DDEXT
CLOCK SIGNALS
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processor can be
clocked by an external crystal, a sine wave input, or a buffered,
shaped clock derived from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the processors include an on-chip oscilla-
tor circuit, an external crystal may be used. For fundamental
frequency operation, use the circuit shown in
parallel-resonant, fundamental frequency, microprocessor-
grade crystal is connected across the CLKIN and XTAL pins.
The on-chip resistance between CLKIN and the XTAL pin is in
the 500 k range. Further parallel resistors are typically not rec-
ommended. The two capacitors and the series resistor shown in
Figure 6
The capacitor and resistor values shown in
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. The user should verify the
customized values based on careful investigations of multiple
devices over temperature range.
A third-overtone crystal can be used for frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in
ation is discussed in detail in application note EE-168.
The CLKBUF pin is an output pin, and is a buffer version of the
input clock. This pin is particularly useful in Ethernet applica-
tions to limit the number of required clock sources in the
system. In this type of application, a single 25 MHz or 50 MHz
crystal may be applied directly to the processors. The 25 MHz or
50 MHz output of CLKBUF can then be connected to an exter-
nal Ethernet MII or RMII PHY device.
VR
V
V
DDEXT
DDINT
OUT
1-0
fine-tune phase and amplitude of the sine frequency.
Figure
NOTE: VR
AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO NDS8434.
100µF
6. A design procedure for third-overtone oper-
Figure 5. Voltage Regulator Circuit
100µF
OUT
1µF
1-0 SHOULD BE TIED TOGETHER EXTERNALLY
EXTERNAL COMPONENTS
0.1µF
ZHCS1000
10µH
NDS8434
Figure 6
Figure
2.25V TO 3.6V
INPUT VOLTAGE
RANGE
are typical
6. A