CP3UB17G38 NSC [National Semiconductor], CP3UB17G38 Datasheet - Page 108

• Manufacturer Part Number: CP3UB17G38
• Description: CP3UB17 Reprogrammable Connectivity Processor with USB Interface
• Manufacturer: NSC [National Semiconductor]

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the UART Frame Select register. The value of the ninth bit
received is read from URB9 in the UART Status Register.
18.2.3
The Diagnostic mode is available for testing of the UART. In
this mode, the TXD and RXD pins are internally connected
together, and data shifted out of the transmit shift register is
immediately transferred to the receive shift register. This
mode supports only the 9-bit data format with no parity. The
number of start and stop bits is programmable.
18.2.4
The format shown in Figure 27 consists of a start bit, seven
data bits (excluding parity), and one or two stop bits. If parity
bit generation is enabled by setting the UPEN bit, a parity bit
is generated and transmitted following the seven data bits.
The format shown in Figure 28 consists of one start bit,
eight data bits (excluding parity), and one or two stop bits. If
parity bit generation is enabled by setting the UPEN bit, a
parity bit is generated and transmitted following the eight
data bits.
The format shown in Figure 29 consists of one start bit, nine
data bits, and one or two stop bits. This format also supports
the UART attention feature. When operating in this format,
all eight bits of UTBUF and URBUF are used for data. The
ninth data bit is transmitted and received using two bits in
2a
2b
2c
2
1a
1b
1c
1
Diagnostic Mode
Frame Format Selection
Figure 27. 7-Bit Data Frame Options
Figure 28. 8-Bit Data Frame Options
Start
Start
Start
Start
Bit
Bit
Bit
Bit
Start
Start
Start
Start
Bit
Bit
Bit
Bit
7-Bit Data
7-Bit Data
7-Bit Data
7-Bit Data
8-Bit Data
8-Bit Data
8-Bit Data
8-Bit Data
PA
1S
PA
PA
1S
PA
2S
2S
1S
1S
2S
2S
DS063
DS064
108
the control registers, called UXB9 and URB9. Parity is not
generated or verified in this mode.
18.2.5
The Baud Rate Generator creates the basic baud clock from
the System Clock. The System Clock is passed through a
two-stage divider chain consisting of a 5-bit baud rate pres-
caler (UPSC) and an 11-bit baud rate divisor (UDIV).
The relationship between the 5-bit prescaler select (UPSC)
setting and the prescaler factors is shown in Table 41.
3a
3
Prescaler Select
Baud Rate Generator
Figure 29. 9-bit Data Frame Options
Start
Start
Bit
Bit
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
Table 41 Prescaler Factors
9-Bit Data
9-Bit Data
Prescaler Factor
No clock
10.5
11.5
12.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10
11
12
13
1
2
3
4
5
6
7
8
9
1S
2S
DS065