CP3UB17G38 NSC [National Semiconductor], CP3UB17G38 Datasheet - Page 50

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CP3UB17G38

Manufacturer Part Number
CP3UB17G38
Description
CP3UB17 Reprogrammable Connectivity Processor with USB Interface
Manufacturer
NSC [National Semiconductor]
Datasheet
www.national.com
11.0 Triple Clock and Reset
The Triple Clock and Reset module generates a 12 MHz
Main Clock and a 32.768 kHz Slow Clock from external
crystal networks or external clock sources. It provides vari-
ous clock signals for the rest of the chip. It also provides the
main system reset signal, a power-on reset function, Main
Main Clock
Reset
X1CKI
X1CKO
X2CKI
X2CKO
(x3, x4, or x5)
32 kHz Osc.
Main Osc.
PLL
TWM (Invalid Watchdog Service)
Flash Interface (Program/Erase Busy)
External Reset
Figure 3. Triple Clock and Reset Module
Stop Main Osc.
by 2
Div.
Slow Clock Prescaler
Preset
Power-On-Reset
Start-Up-Delay
Start-Up-Delay
Module (POR)
14-Bit Timer
8-Bit Timer
Stop PLL
4-Bit Aux1
4-Bit Aux2
50
Prescaler
Prescaler
Prescaler
Preset
8-Bit
Clock prescalers to generate two additional low-speed
clocks, and a 32-kHz oscillator start-up delay.
Figure 3 is block diagram of the Triple Clock and Reset mod-
ule.
Fast Clock
Prescaler
Prescaler
Time-out
4-Bit
Module
Reset
Stop Main Osc
Good Main Clock
Auxiliary Clock 1
Auxiliary Clock 2
Slow Clock
Slow Clock
Select
Good Slow Clock
Stop Slow Osc
Bypass
32 kHz Osc
System Clock
Fast Clock
Select
PLL Clock
Bypass PLL
Good PLL Clock
Stop PLL
Device Reset
Stretched
Reset
DS006

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