CP3UB17G38 NSC [National Semiconductor], CP3UB17G38 Datasheet - Page 26

• Manufacturer Part Number: CP3UB17G38
• Description: CP3UB17 Reprogrammable Connectivity Processor with USB Interface
• Manufacturer: NSC [National Semiconductor]

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6.3
There are four types of data transfer bus cycles:
The type of data cycle used in a particular transaction de-
pends on the type of CPU operation (a write or a read), the
type of memory or I/O being accessed, and the access type
programmed into the BIU control registers (early/late write
or normal/fast read).
For read operations, a basic normal read takes two clock cy-
cles, and a fast-read bus cycle takes one clock cycle. Nor-
mal read bus cycles are enabled by default after reset.
For write operations, a basic late-write bus cycle takes two
clock cycles, and a basic early-write bus cycle takes three
clock cycles. Early-write bus cycles are enabled by default
after reset. However, late-write bus cycles are needed for
ordinary write operations, so this configuration must be
changed by software (see Section 6.4.1).
In certain cases, one or more additional clock cycles are
added to a bus access cycle. There are two types of addi-
tional clock cycles for ordinary memory accesses, called in-
ternal wait cycles (TIW) and hold (T hold ) cycles.
A wait cycle is inserted in a bus cycle just after the memory
address has been placed on the address bus. This gives the
accessed memory more time to respond to the transaction
request.
A hold cycle is inserted at the end of a bus cycle. This holds
the data on the data bus for an extended number of clock cy-
cles.
6.4
The BIU has a set of control registers that determine how
many wait cycles and hold cycles are to be used for access-
ing memory. During initialization of the system, these regis-
ters should be programmed with appropriate values so that
the minimum allowable number of cycles is used. This num-
ber varies with the clock frequency.
There are five BIU control registers, as listed in Table 10.
These registers control the bus cycle configuration used for
accessing the various on-chip memory types.
Normal read
Fast read
Early write
Late write
SZCFG0
SZCFG1
SZCFG2
IOCFG
Name
BCFG
BUS CYCLES
BIU CONTROL REGISTERS
Table 10 Bus Control Registers
FF F900h
FF F902h
FF F904h
FF F906h
FF F908h
Address
BIU Configuration Register
I/O Zone Configuration
Configuration Register
Configuration Register
Configuration Register
Static Zone 0
Static Zone 1
Static Zone 2
Description
Register
26
6.4.1
The BCFG register is a byte-wide, read/write register that
selects early-write or late-write bus cycles. At reset, the reg-
ister is initialized to 07h. The register format is shown below.
EWR
At reset, the BCFG register is initialized to 07h, which se-
lects early-write operation. However, late-write operation is
required for normal device operation, so software must
change the register value to 06h. Bits 1 and 2 of this register
must always be set when writing to this register.
6.4.2
The IOCFG register is a word-wide, read/write register that
controls the timing and bus characteristics of accesses to
the 256-byte I/O Zone memory space (FF FB00h to FF
FBFFh). The registers associated with Port B and Port C re-
side in the I/O memory array. At reset, the register is initial-
ized to 069Fh. The register format is shown below.
WAIT
HOLD
BW
IPST
BW
15
7
7
BIU Configuration Register (BCFG)
I/O Zone Configuration Register (IOCFG)
Reserved
6
Reserved
The Early Write bit controls write cycle timing.
0
1
The Memory Wait Cycles field specifies the
number of TIW (internal wait state) clock cy-
cles added for each memory access, ranging
from 000 binary for no additional TIW wait cy-
cles to 111 binary for seven additional TIW
wait cycles.
The Memory Hold Cycles field specifies the
number of T hold clock cycles used for each
memory access, ranging from 00b for no
T hold cycles to 11b for three T hold clock cy-
cles.
The Bus Width bit defines the bus width of the
IO Zone.
0
1
The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone. No idle
cycles are required for on-chip accesses.
0
1
–
–
–
–
–
–
Reserved
Late-write operation (2 clock cycles to
write).
Early-write operation.
8-bit bus width.
16-bit bus width (default)
No idle cycle (recommended).
Idle cycle.
5
4
HOLD
3
3
10
2
1
2
WAIT
IPST
1
1
9
EWR
Res.
0
0
8