CP3UB17G38 NSC [National Semiconductor], CP3UB17G38 Datasheet - Page 27

• Manufacturer Part Number: CP3UB17G38
• Description: CP3UB17 Reprogrammable Connectivity Processor with USB Interface
• Manufacturer: NSC [National Semiconductor]

6.4.3
The SZCFG0 register is a word-wide, read/write register
that controls the timing and bus characteristics of Zone 0
memory accesses. Zone 0 is used for the on-chip flash
memory (including the boot area, program memory, and
data memory).
At reset, the register is initialized to 069Fh. The register for-
mat is shown below.
WAIT
HOLD
RBE
WBR
BW
FRE
IPST
BW
15
7
WBR
Static Zone 0 Configuration Register (SZCFG0)
Reserved
6
The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG0.FRE bit is set.
The Memory Hold field specifies the number
of T hold clock cycles used for each memory
access, ranging from 00b for no T hold cycles
to 11b for three T hold clock cycles. These bits
are ignored if the SZCFG0.FRE bit is set.
The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. Because the flash pro-
gram memory is required to be 16-bit bus
width, the RBE bit is a don’t care bit. This bit
is ignored when the SZCFG0.FRE bit is set.
0
1
The Wait on Burst Read bit controls if a wait
state is added on burst read transaction. This
bit is ignored, when SZCFG0.FRE bit is set or
when SZCFG0.RBE is clear.
0
1
The Bus Width bit controls the bus width of the
zone. The flash program memory must be
configured for 16-bit bus width.
0
1
The Fast Read Enable bit controls whether
fast read bus cycles are used. A fast read op-
eration takes one clock cycle. A normal read
operation takes at least two clock cycles.
0
1
The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone. No idle
cycles are required for on-chip accesses.
0
1
–
–
–
–
–
–
–
–
–
–
RBE
5
Burst read disabled.
Burst read enabled.
No TBW on burst read cycles.
One TBW on burst read cycles.
8-bit bus width.
16-bit bus width (required).
Normal read cycles.
Fast read cycles.
No idle cycle (recommended).
Idle cycle inserted.
12
4
HOLD
FRE
11
3
IPRE IPST
10
2
WAIT
9
Res.
0
8
27
IPRE
6.4.4
The SZCFG1 register is a word-wide, read/write register
that controls the timing and bus characteristics for off-chip
accesses selected with the SEL1 output signal.
At reset, the register is initialized to 069Fh. The register for-
mat is shown below.
WAIT
HOLD
RBE
WBR
BW
FRE
BW
15
7
WBR
Static Zone 1 Configuration Register (SZCFG1)
Reserved
6
The Preliminary Idle bit controls whether an
idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a dif-
ferent zone. No idle cycles are required for on-
chip accesses.
0
1
The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG1.FRE bit is set.
The Memory Hold field specifies the number
of T hold clock cycles used for each memory
access, ranging from 00b for no T hold cycles
to 11b for three T hold clock cycles. These bits
are ignored if the SZCFG1.FRE bit is set.
The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. This bit is ignored when
the
SZCFG1.BW is clear.
0
1
The Wait on Burst Read bit controls if a wait
state is added on burst read transaction. This
bit is ignored, when SZCFG1.FRE bit is set or
when SZCFG1.RBE is clear.
0
1
The Bus Width bit controls the bus width of the
zone.
0
1
The Fast Read Enable bit controls whether
fast read bus cycles are used. A fast read op-
eration takes one clock cycle. A normal read
operation takes at least two clock cycles.
0
1
–
–
–
–
–
–
–
–
–
–
RBE
No idle cycle (recommended).
Idle cycle inserted.
Burst read disabled.
Burst read enabled.
No TBW on burst read cycles.
One TBW on burst read cycles.
8-bit bus width.
16-bit bus width.
Normal read cycles.
Fast read cycles.
5
SZCFG1.FRE
12
4
HOLD
FRE
11
3
bit
IPRE IPST
10
2
is
www.national.com
WAIT
set
9
or
Res.
0
8
the