CP3UB17G38 NSC [National Semiconductor], CP3UB17G38 Datasheet - Page 58

• Manufacturer Part Number: CP3UB17G38
• Description: CP3UB17 Reprogrammable Connectivity Processor with USB Interface
• Manufacturer: NSC [National Semiconductor]

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12.7.2
Entry into Idle mode is performed by writing a 1 to the PMC-
SR.IDLE bit and then executing a WAIT instruction. The Idle
mode can be entered only from the Active or Power Save
mode. For entry from Active mode, the PMMCR.WBPSM bit
must be set before the WAIT instruction is executed.
12.7.3
When the low-frequency oscillator is used to generate the
Slow Clock, power consumption can be reduced further in
the Power Save or Idle mode by disabling the high-frequen-
cy oscillator. This is accomplished by writing a 1 to the PMC-
SR.DHF bit before executing the WAIT instruction that puts
the device in the Power Save or Idle mode. The high-fre-
quency clock is turned off only after the device enters the
Power Save or Idle mode.
The CPU operates on the low-frequency clock in Power
Save mode. It can turn off the high-frequency clock at any
time by writing a 1 to the PMCSR.DHF bit. The high-fre-
quency oscillator is always enabled in Active mode and al-
ways disabled in Halt mode, without regard to the
PMCSR.DHF bit setting.
Immediately after power-up and entry into Active mode,
software must wait for the low-frequency clock to become
stable before it can put the device in Power Save mode. It
should monitor the PMCSR.OLC bit for this purpose. Once
this bit is set, Slow Clock is stable and Power Save mode
can be entered.
12.7.4
Entry into Halt mode is accomplished by writing a 1 to the
PMCSR.HALT bit and then executing a WAIT instruction.
Halt mode can be entered only from Active or Power Save
mode. For entry from Active mode, the PMCSR.WBPSM bit
must be set before the WAIT instruction is executed.
12.7.5
A transition from Power Save mode to Active mode can be
accomplished by either a software command or a hardware
wake-up event. The software method is to write a 0 to the
PMCSR.PSM bit. The value of the register bit changes only
after the transition to the Active mode is completed.
If the high-frequency oscillator is disabled for Power Save
operation, the oscillator must be enabled and allowed to sta-
bilize before the transition to Active mode. To enable the
high-frequency oscillator, software writes a 0 to the PMC-
SR.DMC bit. Before writing a 0 to the PMCSR.PSM bit, soft-
ware must first monitor the PMCSR.OMC bit to determine
when the oscillator has stabilized.
Disabling the High-Frequency Clock
Entering Idle Mode
Entering Halt Mode
Software-Controlled Transition to Active Mode
58
12.7.6
A hardware wake-up event switches the device directly from
Power Save, Idle, or Halt mode to Active mode. Hardware
wake-up events are:
When a wake-up event occurs, the on-chip hardware per-
forms the following steps:
12.7.7
The Power Management Module has several mechanisms
to protect the device from malfunctions caused by missing
or unstable clock signals.
The PMCSR.OHC, PMCSR.OMC, and PMCSR.OLC bits
indicate the current status of the PLL, high-frequency oscil-
lator, and low-frequency oscillator, respectively. Software
can check the appropriate bit before switching to a power
mode that requires the clock. A set status bit indicates an
operating, stable clock. A clear status bit indicates a clock
that is disabled, not available, or not yet stable. (Except in
the case of the PLL, which has a set status bit when dis-
abled.)
During a power mode transition, if there is a request to
switch to a mode with a clear status bit, the switch is delayed
until that bit is set by the hardware.
When the system is built without an external crystal network
for the low-frequency clock, Main Clock is divided by a pres-
caler factor to produce the low-frequency clock. In this situ-
ation, Main Clock is disabled only in the Halt mode, and
cannot be disabled for the Power Save or Idle mode.
Without an external crystal network for the low-frequency
clock, the device comes out of Halt or Idle mode and enters
Active mode with Main Clock driving Slow Clock.
Note: For correct operation in the absence of a low-fre-
quency crystal, the X2CKI pin must be tied low (not left float-
ing) so that the hardware can detect the absence of the
crystal.
1. Clears the PMCSR.DMC bit, which enables the high-
2. Waits for the PMCSR.OMC bit to become set, which in-
3. Clears the PMCSR.DHC bit, which enables the PLL.
4. Waits for the PMCSR.OHC bit to become set.
5. Switches the device into Active mode.
Non-Maskable Interrupt (NMI)
Valid wake-up event on a Multi-Input Wake-Up channel
frequency clock (if it was disabled).
dicates that the high-frequency clock is operating and
is stable.
Wake-Up Transition to Active Mode
Power Mode Switching Protection