CP3UB17G38 NSC [National Semiconductor], CP3UB17G38 Datasheet - Page 114

• Manufacturer Part Number: CP3UB17G38
• Description: CP3UB17 Reprogrammable Connectivity Processor with USB Interface
• Manufacturer: NSC [National Semiconductor]

www.national.com
18.4
The UART baud rate is determined by the System Clock fre-
quency and the values in the UOVR, UPSR, and UBAUD
registers. Unless the System Clock is an exact multiple of
the baud rate, there will be a small amount of error in the re-
sulting baud rate. The equation to calculate the baud rate is:
where BR is the baud rate, SYS_CLK is the System Clock,
O is the oversample rate, N is the the baud rate divisor + 1,
and P is the prescaler divisor selected by the UPSR register.
Assuming a System Clock of 5 MHz, a desired baud rate of
9600, and an oversample rate of 16, the N × P term accord-
ing to the equation above is:
1105920
1382400
1536000
115200
128000
230400
345600
460800
576000
691200
806400
921600
14400
19200
38400
56000
Baud
Rate
1200
1800
2000
2400
3600
4800
7200
9600
300
600
BAUD RATE CALCULATIONS
N P
16
16
16
16
16
16
12
16
11
10
10
15
13
13
10
13
11
10
×
O
7
8
7
7
9
8
7
9
SYS_CLK = 48 MHz
BR
=
2000
2000
1250
1500
1250
1111
401
625
101
125
202
250
125
49
17
25
16
N
------------------------------ -
(
1
8
7
7
1
4
4
1
1
16
=
(
5
×
----------------------------- -
(
×10
SYS_CLK
O N
15.5 0.44
9600
5.0
2.5
2.0
9.5
1.0
1.0
1.5
1.0
5.5
2.5
1.5
1.0
1.0
2.5
3.5
1.0
1.0
1.0
1.5
1.0
8.5
1.0
1.0
3.5
3.5
P
×
6
)
)
×
%err
0.00
0.00
0.00
0.00
0.00
0.00
0.01
0.00
0.01
0.00
0.01
0.00
0.00
0.04
0.04
0.00
0.16
0.16
0.79
0.79
0.04
0.16
1.36
0.79
0.79
=
P
)
32.552
Table 43 Baud Rate Programming
16
16
16
16
16
12
16
11
10
11
10
10
13
13
15
13
10
13
12
10
15
13
11
O
8
7
8
SYS_CLK = 24 MHz
2000
1250
1250
1111
750
625
101
125
303
250
101
125
25
33
16
N
5
8
7
4
1
1
2
2
2
1
2
2.5
2.0
1.0
1.5
1.0
1.0
5.5
2.5
1.0
1.0
1.5
1.0
2.5
1.0
1.0
2.5
1.0
1.0
1.0
3.5
3.5
1.0
1.0
1.0
2.5
1.0
P
114
%err
The N × P term is then divided by each Prescaler Factor
from Table 41 to obtain a value closest to an integer. The
factor for this example is 6.5.
The baud rate register is programmed with a baud rate divi-
sor of 4 (N = baud rate divisor + 1). This produces a baud
clock of:
Note that the percent error is much lower than would be pos-
sible without the non-integer prescaler factor. Error greater
than 3% is marginal and may result in unreliable operation.
Refer to Table 43 below for more examples.
0.00
0.00
0.00
0.01
0.00
0.00
0.01
0.00
0.01
0.00
0.01
0.00
0.00
0.10
0.16
0.00
0.16
0.79
0.16
0.79
0.79
0.79
0.16
1.36
0.79
2.34
16
16
16
12
16
16
11
10
11
10
14
10
16
13
13
11
13
10
13
14
10
13
O
7
SYS_CLK = 12 MHz
%error
BR
1250
1250
625
101
250
125
202
250
101
125
N
17
25
13
11
N
8
1
4
1
2
1
1
1
1
=
=
32.552
----------------- -
=
-----------------------------------
(
16 5
2.0
1.0
1.0
5.5
1.5
2.5
1.5
1.0
1.5
1.0
3.5
2.5
1.5
1.5
1.0
8.5
1.0
3.5
1.0
1.5
2.5
1.5
1.0
6.5
P
(
------------------------------------------------ -
(
9615.385 9600
5
×
×10
%err
0.00
0.00
0.00
0.01
0.00
0.00
0.01
0.00
0.01
0.00
0.04
0.00
0.16
0.10
0.16
0.27
0.16
0.79
0.16
0.79
0.79
0.79
0.16
×
=
6
9600
6.5
)
5.008 (N = 5)
)
–
13
13
13
12
16
11
10
14
16
12
11
11
=
O
9
7
7
8
7
7
7
9
SYS_CLK = 10 MHz
9615.385
1282
1282
)
641
463
125
463
101
119
139
149
33
13
13
17
N
5
1
4
2
1
1
=
0.16
2.0
1.0
1.0
1.0
2.5
1.0
2.5
2.5
1.0
1.0
1.5
2.5
2.5
1.5
2.5
6.5
1.0
1.0
2.5
1.0
P
%err
0.00
0.00
0.00
0.01
0.00
0.01
0.01
0.04
0.08
0.13
0.21
0.16
0.16
0.04
0.79
0.16
1.36
1.36
0.79
0.47