MC68HC08AZ60CFU MOTOROLA [Motorola, Inc], MC68HC08AZ60CFU Datasheet - Page 162

• Manufacturer Part Number: MC68HC08AZ60CFU
• Description: Advance Information
• Manufacturer: MOTOROLA [Motorola, Inc]

Low-Voltage Inhibit (LVI)
Polled LVI
Operation
Forced Reset
Operation
False Reset
Protection
MC68HC08AZ60 — Rev 1.0
162
$FE0F
Addr.
Register Name
LVI Status Register (LVISR) LVIOUT
In applications that can operate at V
software can monitor V
register, the LVIPWR bit must be at logic 1 to enable the LVI module, and
the LVIRST bit must be at logic 0 to disable LVI resets.
In applications that require V
enabling LVI resets allows the LVI module to reset the MCU when V
falls to the LVI
more consecutive CPU cycles. In the mask option register, the LVIPWR
and LVIRST bits must be at logic 1 to enable the LVI module and to
enable LVI resets.
The V
supply noise. In order for the LVI module to reset the MCU,V
remain at or below the LVI
cycles. V
MCU out of reset.
Freescale Semiconductor, Inc.
Figure 2. LVI I/O Register Summary
For More Information On This Product,
DD
DD
pin level is digitally filtered to reduce false resets due to power
must be above LVI
Go to: www.freescale.com
Bit 7
Low-Voltage Inhibit (LVI)
TRIPF
= Unimplemented
level and remains at or below that level for nine or
6
DD
by polling the LVIOUT bit. In the mask option
TRIPF
DD
5
TRIPR
to remain above the LVI
level for nine or more consecutive CPU
DD
for only one CPU cycle to bring the
4
levels below the LVI
3
2
TRIPF
1
TRIPF
MOTOROLA
DD
level,
must
level,
Bit 0
DD
4-lvi