MC68HC08AZ60CFU MOTOROLA [Motorola, Inc], MC68HC08AZ60CFU Datasheet - Page 229

• Manufacturer Part Number: MC68HC08AZ60CFU
• Description: Advance Information
• Manufacturer: MOTOROLA [Motorola, Inc]

Queuing Transmission Data
19-spi
MOTOROLA
SPSCK (CPHA:CPOL = 1:0)
WRITE TO SPDR
READ SPSCR
READ SPDR
1
2
3
4
5
6
SPRF
CPU WRITES BYTE 1 TO SPDR, CLEARING
SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING
BYTE 2 AND CLEARING SPTE BIT.
FIRST INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU READS SPSCR WITH SPRF BIT SET.
SPTE
MOSI
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE in SPSCR) indicates
when the transmit data buffer is ready to accept new data. Write to the
SPI data register only when the SPTE bit is high.
timing associated with doing back-to-back transmissions with the SPI
(SPSCK has CPHA:CPOL = 1:0).
Figure 9. SPRF/SPTE CPU Interrupt Timing
1
Freescale Semiconductor, Inc.
For More Information On This Product,
Serial Peripheral Interface Module (SPI)
MSB BIT
BYTE 1
Go to: www.freescale.com
2
6
BIT
5
3
BIT
4
BIT
3
BIT
2
BIT
1
10
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
7
8
9
LSB MSB BIT
5
4
CPU READS SPDR, CLEARING SPRF BIT.
CPU WRITES BYTE 3 TO SPDR, QUEUEING
BYTE 3 AND CLEARING SPTE BIT.
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
BYTE 2
6
6
Serial Peripheral Interface Module (SPI)
7
BIT
5
8
BIT
4
BIT
3
MC68HC08AZ60 — Rev 1.0
BIT
Queuing Transmission Data
2
Figure 9
BIT
1
LSB MSB BIT
10
9
BYTE 3
11
shows the
6
12
BIT
5
BIT
4
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