PIC18F1220 MICROCHIP [Microchip Technology], PIC18F1220 Datasheet - Page 186
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PIC18F1220
Manufacturer Part Number
PIC18F1220
Description
18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F1220.pdf
(310 pages)
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PIC18F1220/1320
19.4.4
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or Low-Power Sleep mode. When the primary
system clock is EC, RC or INTRC modes, monitoring
can begin immediately following these events.
For oscillator modes involving a crystal or resonator
(HS, HSPLL, LP or XT), the situation is somewhat dif-
ferent. Since the oscillator may require a start-up time
considerably longer than the FCSM sample clock time,
a false clock failure may be detected. To prevent this,
the internal oscillator block is automatically configured
as the system clock and functions until the primary
clock is stable (the OST and PLL timers have timed
out). This is identical to Two-Speed Start-up mode.
Once the primary clock is stable, the INTRC returns to
its role as the FSCM source
DS39605C-page 184
POR OR WAKE FROM SLEEP
As noted in Section 19.3.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an alter-
nate power managed mode while waiting for the
primary system clock to become stable. When the new
powered managed mode is selected, the primary clock
is disabled.
Note:
The same logic that prevents false oscilla-
tor failure interrupts on POR or wake from
Sleep will also prevent the detection of the
oscillator’s failure to start at all following
these events. This can be avoided by
monitoring the OSTS bit and using a
timing routine to determine if the oscillator
is taking too long to start. Even so, no
oscillator failure interrupt will be flagged.
2004 Microchip Technology Inc.
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