PIC18F1220 MICROCHIP [Microchip Technology], PIC18F1220 Datasheet - Page 211
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PIC18F1220
Manufacturer Part Number
PIC18F1220
Description
18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F1220.pdf
(310 pages)
Available stocks
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Quantity
Price
Part Number:
PIC18F1220-E/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F1220-I/P
Manufacturer:
Microchip Technology
Quantity:
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CPFSGT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2004 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
W
If REG
If REG
Q1
Q1
Q1
No
No
No
PC
PC
register ‘f’
operation
operation
operation
Compare f with W, skip if f > W
[ label ] CPFSGT
0
a
(f) – W),
skip if (f) > (W)
(unsigned comparison)
None
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If the contents of ‘f’ are greater than
the contents of WREG
fetched instruction is discarded and
a NOP is executed instead, making
this a two-cycle instruction. If ‘a’ is
‘0’, the Access Bank will be
selected, overriding the BSR value.
If ‘a’ = 1, then the bank will be
selected as per the BSR value
(default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NGREATER
GREATER
Read
0110
Q2
Q2
Q2
No
No
No
=
=
=
=
f
[0,1]
255
by a 2-word instruction.
Address (HERE)
?
W;
Address (GREATER)
W;
Address (NGREATER)
010a
CPFSGT REG
:
:
operation
operation
operation
Process
Data
Q3
Q3
Q3
No
No
No
ffff
f [,a]
,
then the
operation
operation
operation
operation
Q4
Q4
Q4
No
No
No
No
ffff
CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
W
If REG
If REG
Q1
Q1
Q1
PIC18F1220/1320
No
No
No
PC
PC
register ‘f’
operation
operation
operation
Compare f with W, skip if f < W
[ label ] CPFSLT
0
a
(f) – W),
skip if (f) < (W)
(unsigned comparison)
None
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If the contents of ‘f’ are less than
the contents of W, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected. If ‘a’
is ‘1’, the BSR will not be
overridden (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NLESS
LESS
Read
0110
Q2
Q2
Q2
No
No
No
=
=
<
=
=
f
[0,1]
255
by a 2-word instruction.
Address (HERE)
?
W;
Address (LESS)
W;
Address (NLESS)
CPFSLT REG
:
:
000a
operation
operation
operation
Process
Data
Q3
Q3
Q3
No
No
No
DS39605C-page 209
ffff
f [,a]
operation
operation
operation
operation
Q4
Q4
Q4
No
No
No
No
ffff
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