NHPXA270CXXX INTEL [Intel Corporation], NHPXA270CXXX Datasheet - Page 100
NHPXA270CXXX
Manufacturer Part Number
NHPXA270CXXX
Description
Electrical, Mechanical, and Thermal Specification
Manufacturer
INTEL [Intel Corporation]
Datasheet
1.NHPXA270CXXX.pdf
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Intel® PXA270 Processor
AC Timing Specifications
6.4.6
6-36
nCSx or nSDCSx
nADV(nSDCAS)
Figure 6-23. 16-bit SRAM Write for 4/2/1 Byte(s) Timing
DQM<1:0>
CLK_MEM
MD<15:0>
MA<25:1>
Note:
nCS<2>
RDnWR
MA<0>
nWE
nOE
Variable-Latency I/O Parameters and Timing Diagrams
The following sections describe the read/write parameters and timing diagrams for VLIO memory
interfaces with the memory controller.
Table 6-20
Table 6-20
“Memory Controller” chapter in the Intel® PXA27x Processor Family Developer’s Manual for
register configurations.
tramAS
addr
lists the timing-information references for both the read and the write timing diagrams.
lists programmable register items. For more information on these items, see the
Bytes 1:0
'0'
tsramCES
32-bit Write
0b00
tsramWL
tsramDSWH
tsramAH
tsramDH
Bytes 3:2
tsramASW
addr+1
NOTE: MSC1[RDF2]=1, MSC1[RDN]=2, MSC1[RRR2]=2
'0'
tsramWL
tsramWL
tsramDSWH
tsramCEH
tsramDH
tsramCD
16-bit Write
tramAS
Electrical, Mechanical, and Thermal Specification
Bytes 1:0
tsramCES
0b00
addr
'0'
tsramWL
tsramDSWH
tsramCEH
tsramDH
tsramCD
tramAS
8-bit Write
Byte 0 OR 1
0b01 / 0b10
'0' or '1'
tsramCES
addr
tsramWL
tsramDSWH
tsramCEH
tsramDH
tsramCD
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