NHPXA270CXXX INTEL [Intel Corporation], NHPXA270CXXX Datasheet - Page 49
NHPXA270CXXX
Manufacturer Part Number
NHPXA270CXXX
Description
Electrical, Mechanical, and Thermal Specification
Manufacturer
INTEL [Intel Corporation]
Datasheet
1.NHPXA270CXXX.pdf
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4.5
Electrical, Mechanical, and Thermal Specification
Table 4-4. Memory Controller Pin Reset Values (Sheet 2 of 2)
Table 4-5. Discrete (13x13 VF-BGA) Power Supply Pin Summary
The address signals are driven low and data signals are pulled low during sleep, standby, deep-
sleep, frequency-change modes, and manual self-refresh. All other memory control signals are in
the same state that they are in after a hardware reset. If the SDRAMs are in self-refresh mode, they
are kept there by driving SDCKE low.
Power-Supply Pins
Table 4-5
nPOE
nPWE
NOTE:
† This indicates that the GPIO pin, if configured for the alternate function
NOTE: SCLK<3> is only available on PXA270 processor family packages
Name
VCC_BATT
VCC_IO
VCC_USB
VCC_LCD
VCC_MEM
VCC_BB
VCC_PLL
VCC_SRAM
VCC_CORE
VCC_USIM
VSS
VSS_IO
VSS_MEM
VSS_BB
VSS_PLL
VSS_CORE
1. MA pins are driven
2. MD pins are pulled low
used by the memory controller during reset, drives the represented
value.
Pin Name
summarize the power-supply ball count.
Reset, Sleep, Standby, Deep-Sleep, Frequency
Change, and Manual Self-Refresh Mode Values
GPIO (memory controller drives high)
GPIO (memory controller drives high)
Number of Package Balls
13x13 mm VF-BGA
19
14
17
56
1
3
4
2
1
1
4
1
6
9
1
1
§§
Pin Listing and Signal Definitions
Number of Pachage Balls
23x23 mm PBGA
Intel® PXA270 Processor
16
20
17
56
1
3
4
2
1
1
4
1
5
9
1
1
4-29
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