NHPXA270CXXX INTEL [Intel Corporation], NHPXA270CXXX Datasheet - Page 104

• Manufacturer Part Number: NHPXA270CXXX
• Description: Electrical, Mechanical, and Thermal Specification
• Manufacturer: INTEL [Intel Corporation]

Intel® PXA270 Processor
AC Timing Specifications
6.4.7
6-40
Symbols
tcdAVCL
tcdCHAI
tcdDVCL
tcdCHWDI
tcdDVCH
tcdCHRDI
tcdCMD
tcdILCL
tcdCHIH
tcdCLPS
tcdPHCH
NOTES:
1. All numbers shown are ideal, integer multiples of the CLK_MEM period. Actual numbers vary with pin-to-pin differences in
2. Includes signals MA[25:0], nPREG, and nPSKTSEL.
3. CMD refers to signals nPWE, nPOE, nPIOW, and nPIOR
4. Refer to the Intel® PXA27x Processor Family Developer’s Manual, Expansion Memory Timing Configuration registers to
5. Refer to the Intel® PXA27x Processor Family Developer’s Manual, Expansion Memory Timing Configuration registers to
6. Refer to the Intel® PXA27x Processor Family Developer’s Manual, Expansion Memory Timing Configuration registers to
7. tcdCLPS equals CLK_MEM * x_ASST_WAIT. Refer to the PC Card Interface Command Assertion Code table in the Intel®
8. tcdPHCH equals CLK_MEM * x_ASST_HOLD. Refer to the PC Card Interface Command Assertion Code table in the Intel®
loading and transition direction (rise or fall).
change the assertion of CMD using the MCx[SET] bit fields.
increase the assertion of CMD using the MCx[HOLD] bit fields.
increase timings. The timings are changed by programming the MCx[ASST] respective bit fields. Refer to the PC Card
Interface Command Assertion Code table to see the effect of MCx[ASST].
PXA27x Processor Family Developer’s Manual for the correlation between x_ASST_WAIT and the MCx[ASST] bit field.
PXA27x Processor Family Developer’s Manual for the correlation between x_ASST_HOLD and the MCx[ASST] bit field.
Table 6-21. Expansion-Card Interface AC Specifications
Note:
Expansion-Card Interface Parameters and Timing Diagrams
The following sections describe the read/write parameters and timing diagrams for CompactFlash*
and PC Card* (expansion card) memory interfaces with the memory controller.
Table 6-21
Table 6-21
PXA27x Processor Family Developer’s Manual for register configurations for more information on
these items.
Parameters
Address Valid to CMD Low
CMD High to Address Invalid
Write Data Valid to CMD Low
CMD High to Write Data Invalid
Read Data Valid to CMD High
CMD High to Read Data Invalid
CMD Assert During Transfers
nIOIS16 Low to CMD Low
CMD High to nIOIS16 High
CMD Low to nPWAIT Sample
nPWAIT High to CMD High
shows the timing parameters used in the timing diagrams,
lists programmable register items. See the “Memory Controller” chapter in the Intel®
MIN
—
—
—
—
—
2
0
2
0
4
2
Electrical, Mechanical, and Thermal Specification
x_ASST_HOLD
x_ASST_WAIT
MCx[HOLD]
tcdPHCH +
tcdCLPS +
MCx[SET]
assertion
nPWAIT
TYP
—
—
—
—
1
4
MAX
127
63
—
—
—
—
—
—
—
—
—
Figure 6-26
CLK_MEM
CLK_MEM
CLK_MEM
CLK_MEM
CLK_MEM
CLK_MEM
CLK_MEM
CLK_MEM
CLK_MEM
CLK_MEM
Units
ns
and
Figure
1,2,3,4
1,2,3,5
1,3,6,7
1,3,6,8
Notes
6-27.
1,3
1,3
1,3
1,3
1,3
1,3
3