NHPXA270CXXX INTEL [Intel Corporation], NHPXA270CXXX Datasheet - Page 97

• Manufacturer Part Number: NHPXA270CXXX
• Description: Electrical, Mechanical, and Thermal Specification
• Manufacturer: INTEL [Intel Corporation]

6.4.5
6.4.5.1
6.4.5.2
Electrical, Mechanical, and Thermal Specification
Figure 6-21. 16-Bit Flash Write Timing
nCSx or nSDCSx
nADV(nSDCAS)
CLK_MEM
MD<15:0>
MA<25:1>
DQM<1:0>
nCS<2>
RDnWR
MA<0>
SRAM Parameters and Timing Diagrams
The following sections describe the read/write parameters and timing diagrams for SRAM
interfaces with the memory controller.
SRAM Read Parameters and Timing Diagrams
The timing for a read access is identical to that for a non-burst ROM read (see
timings listed in
Figure 6-14
during read-bus tenures.
SRAM Write Parameters and Timing Diagrams
Figure 6-22
the timings used in
nWE
nOE
NOTE: MSC1[RDN2] = 2, MSC1[RDF2] = 1, MSC1[RRR2] = 2
for timings diagrams representing 16-bit SRAM transferring four, two, and one byte(s)
and
Figure 6-23
Table 6-16
Figure 6-22
Applies to:
16-bit Non-Burst Flash
16-bit Burst Flash
tflashAS
for ROM reads are also used for SRAM reads. See
show the timing for 32-bit and 16-bit SRAM writes.
and
Figure
tflashCES
Bytes 1:0
0b00
addr
0b0
6-23.
tflashWL
tflashDSWH
tflashCEH
tflashDH
tflashCD
AC Timing Specifications
Intel® PXA270 Processor
Figure
Figure 6-11
Table 6-19
6-11). The
and
lists
6-33