NHPXA270CXXX INTEL [Intel Corporation], NHPXA270CXXX Datasheet - Page 29

• Manufacturer Part Number: NHPXA270CXXX
• Description: Electrical, Mechanical, and Thermal Specification
• Manufacturer: INTEL [Intel Corporation]

4.2
Electrical, Mechanical, and Thermal Specification
Figure 4-8. 23x23 mm PBGA Ball Map, Top View (Lower Right Quarter)
Pin Usage
The pin usage summary shown in
through R15 (VF-BGA) or J9 through P14 (PBGA), all of which function as VSS_CORE (see the
recommendations for connecting the 36 center balls in the Intel® PXA27x Processor Family
Design Guide).
Each signal’s alternate function inputs are shown in the upper section of each signal row and the
outputs are shown in the lower section of each signal row. For example, GPIO<48> has a primary
input function of CIF_DD<5> and a secondary output function of nPOE.
VSS_CORE VSS_CORE VSS_CORE
VSS_CORE VSS_CORE VSS_CORE
VSS_CORE VSS_CORE VSS_CORE
GPIO[50]
GPIO[52]
GPIO[53]
GPIO[51]
12
GPIO[106]
GPIO[105]
GPIO[108]
GPIO[54]
13
VSS_CORE VCC_CORE VSS_CORE VCC_CORE VSS_CORE BOOT_SEL
GPIO[104]
GPIO[102]
GPIO[107]
VSS_IO
14
GPIO[100]
GPIO[103]
GPIO[97]
VCC_IO
15
GPIO[101]
Table 4-1
GPIO[96]
GPIO[93]
GPIO[98]
16
VCC_BATT
PWR_CAP
GPIO[94]
GPIO[99]
does not include the 36 center balls identified as K10
17
[3]
VCC_CORE
VCC_CORE
VSS_CORE
VSS_CORE
PWR_CAP
GPIO[95]
VSS_IO
VSS
18
[2]
NBATT_FAU
PWR_OUT
PWR_CAP
VCC_LCD
VSS_PLL
VCC_PLL
GPIO[19]
Pin Listing and Signal Definitions
VSS_IO
GPIO[4]
TCK
19
LT
[0]
NVDD_FAUL
PXTAL_OUT
PXTAL_IN
GPIO[86]
GPIO[75]
GPIO[14]
NRESET
GPIO[0]
NTRST
TMS
VSS
Intel® PXA270 Processor
20
T
NRESET_O
PWR_CAP
CLK_REQ
TXTAL_IN
GPIO[76]
GPIO[77]
SYS_EN
VSS_IO
GPIO[1]
TDO
VSS
UT
21
[1]
TXTAL_OUT
TESTCLK
PWR_EN
GPIO[87]
GPIO[74]
GPIO[10]
GPIO[9]
GPIO[3]
VSS
VSS
TDI
22
AA
AB
M
W
N
P
R
T
U
V
Y
4-9