NHPXA270CXXX INTEL [Intel Corporation], NHPXA270CXXX Datasheet - Page 89

• Manufacturer Part Number: NHPXA270CXXX
• Description: Electrical, Mechanical, and Thermal Specification
• Manufacturer: INTEL [Intel Corporation]

Electrical, Mechanical, and Thermal Specification
tffSDIS
tffSDIH
NOTES:
Symbols
1. SDCLK0 may be configured to be CLK_MEM divided by 1, 2 or 4. SDCLK0 for synchronous flash memory can be at the slowest,
2. SDCLK0 frequency equals CLK_MEM frequency (MDREFR[K0DB4] and MDREFR[K0DB2] bit fields are clear)
3. SDCLK0 frequency equals CLK_MEM/2 frequency (MDREFR[K0DB2] is set and MDREFR[K0DB4] is clear).
4. SDCLK0 frequency equals CLK_MEM/4 frequency (MDREFR[K0DB4] is set).
5. Use SXCNFG[SXCLx] to configure the value for the frequency configuration code (FCC).
6. These numbers are for VCC_MEM = 1.8 V +20% / -5%, VOL = 0.4 V, and VOH = 1.4 V, with each applicable 4-bit field of the
7. These numbers are for VCC_MEM = 2.5 V +/– 10%, VOL = 0.4 V, and VOH = 2.1 V, with each applicable 4-bit field of the system
8. These numbers are for VCC_MEM = 3.3 V +/– 10%, VOL = 0.4 V, and VOH = 2.4 V, with each applicable 4-bit field of the system
divide-by-4 of the 26-MHz CLK_MEM. The fastest possible SDCLK0 is accomplished by configuring CLK_MEM at 104 MHz and
clearing the MDREFR[K0DB2] or MDREFR[K0DB4] bit fields.
system memory buffer strength registers (BSCN TRP and BSCNTRN) set to TBD (msb:lsb) and each applicable SDCLK0 divide-
by-2 and divide-by-4 register bits (MDREFR[K0DB2] and MDREFR[K0DB4]) clear. If MDREFR[K0DB2 is set, the corresponding
output setup and hold times are increased and decreased, respectively, by 0.25 times the SDCLK0 period.
memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK0 divide-by-2
and divide-by-4 register bit (MDREFR[K0DB2] and MDREFR[K0DB4]) clear. If MDREFR[K0DB2 is set, the corresponding output
setup and hold times are increased and decreased, respectively, by 0.25 times the SDCLK0 period.
memory buffer strength registers (BSCNTRP and BSCNTRN) set to 0b1010 (msb:lsb) and each applicable SDCLK0 divide-by-2
and divide-by-4 register bit (MDREFR[K0DB2] and MDREFR[K0DB4]) clear. If MDREFR[K0DB2 is set, the corresponding output
setup and hold times are increased and decreased, respectively, by 0.25 times the SDCLK0 period.
Table 6-17. Synchronous Flash Read AC Specifications (Sheet 2 of 2)
MD<31:0> read
data input setup
time from
SDCLK<2:0> rise
MD<31:0> read
data input hold time
from SDCLK<2:0>
rise
Parameters
TBD
TBD
MIN
TYP
—
—
MAX MIN
—
—
0.5
1.8
TYP
—
—
MAX
—
—
MIN
0.5
1.8
AC Timing Specifications
Intel® PXA270 Processor
TYP
—
—
MAX
—
—
Units
ns
ns
6-25
—
—