MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 112

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MC68HC705P9CDW

Manufacturer Part Number
MC68HC705P9CDW
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Timer
9.7.3 Timer Registers
Technical Data
112
NOTE:
$0018
Read:
Write:
Reset:
$0019
Read:
Write:
Reset:
The read-only timer registers (TRH and TRL) contain the current high
and low bytes of the 16-bit counter. Reading TRH before reading TRL
causes TRL to be latched until TRL is read. Reading TRL after reading
the timer status register clears the timer overflow flag (TOF). Writing to
the timer registers has no effect.
Reading TRH returns the current value of the high byte of the counter
and causes the low byte to be latched into a buffer. The buffer value
remains fixed even if the high byte is read more than once. Reading TRL
reads the transparent low byte buffer and completes the read sequence
of the timer registers.
To prevent interrupts from occurring between readings of TRH and TRL,
set the interrupt mask (I bit) in the condition code register before reading
TRH, and clear the mask after reading TRL.
Freescale Semiconductor, Inc.
For More Information On This Product,
Bit 15
Bit 7
Bit 7
Bit 7
Figure 9-12. Timer Registers (TRH and TRL)
Go to: www.freescale.com
INTERNAL
DATA BUS
= Unimplemented
READ TRH
Figure 9-13. Timer Register Reads
14
6
6
6
Timer
13
5
5
5
LATCH
Reset initializes TRH to $FF
Reset initializes TRL to $FC
TRH ($0018)
12
4
4
4
11
3
3
3
TRL ($0019)
BUFFER
MC68HC705P9 — Rev. 4.0
10
2
2
2
1
9
1
1
MOTOROLA
Bit 0
Bit 8
Bit 0
Bit 0

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