MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 125
MC68HC705P9CDW
Manufacturer Part Number
MC68HC705P9CDW
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC68HC705P9CDW.pdf
(160 pages)
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10.6 Interrupts
10.7 I/O Registers
10.7.1 SIOP Control Register
MC68HC705P9 — Rev. 4.0
MOTOROLA
NOTE:
The SIOP does not generate interrupt requests.
The following registers control and monitor SIOP operation:
The read/write SIOP control register (SCR) contains two bits. One bit
enables the SIOP, and the other configures the SIOP for master mode
or for slave mode.
SPE — SIOP Enable
After clearing SPE, be sure to initialize the port for its intended I/O use.
$000A
Reset:
Read:
Write:
•
•
•
This read/write bit enables the SIOP. Setting SPE initializes the data
direction register as follows:
Clearing SPE disables the SIOP and returns the port to its normal I/O
functions. The data direction register and the port data register remain
in their SIOP-initialized state.
Freescale Semiconductor, Inc.
For More Information On This Product,
•
•
•
SIOP control register (SCR)
SIOP status register (SSR)
SIOP data register (SDR)
Bit 7
The PB6/SDI pin is an input.
The PB5/SDO pin is an output.
The PB7/SCK pin is an input in slave mode and an output in
master mode.
0
0
Serial Input/Output Port (SIOP)
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Figure 10-6. SIOP Control Register (SCR)
SPE
6
0
5
0
0
MSTR
4
0
3
0
0
Serial Input/Output Port (SIOP)
2
0
0
1
0
0
Technical Data
Interrupts
Bit 0
0
0
125
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