MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 121

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MC68HC705P9CDW

Manufacturer Part Number
MC68HC705P9CDW
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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10.4.1.1 PB7/SCK
MC68HC705P9 — Rev. 4.0
MOTOROLA
NOTE:
When bit 6 (SPE) of the SIOP control register (SCR) is set, the SIOP is
enabled and the PB7/SCK, PB5/SDO, and PB6/SDI pins are dedicated
to SIOP functions. Clearing SPE disables the SIOP and the SIOP pins
become standard I/O port pins.
Enabling and then disabling the SIOP configures the data direction
register bits associated with the SIOP pins for SIOP operation and can
also change the associated port data register. After disabling the SIOP,
initialize the data direction register and the port data register as the
application requires.
The PB7/SCK pin synchronizes the movement of data into and out of the
MCU through the PB6/SDI and PB5/SDO pins. In master mode, the
PB7/SCK pin is an output. The serial clock frequency in master mode is
one-fourth the internal clock frequency.
In slave mode, the PB7/SCK pin is an input. The maximum serial clock
frequency in slave mode is one-fourth the internal clock rate. Slave
mode has no minimum serial clock frequency.
Figure 10-3
input, and data output. The state of the serial clock between
transmissions is a logic one. The first falling edge on the PB7/SCK pin
signals the beginning of a transmission, and data appears at the
PB5/SDO pin. Data is captured at the PB6/SDI pin on the rising edge of
the serial clock, and the transmission ends on the eighth rising edge of
the serial clock.
Freescale Semiconductor, Inc.
(MSB-FIRST OPTION)
(LSB-FIRST OPTION)
For More Information On This Product,
SERIAL CLOCK
SAMPLE INPUT
DATA OUTPUT
DATA OUTPUT
Serial Input/Output Port (SIOP)
Go to: www.freescale.com
shows the timing relationships among the serial clock, data
Figure 10-3. SIOP Data/Clock Timing
MSB
LSB
BIT 6
BIT 1
BIT 5
BIT 2
BIT 4
BIT 3
BIT 3
BIT 4
Serial Input/Output Port (SIOP)
BIT 2
BIT 5
BIT 1
BIT 6
Technical Data
MSB
LSB
Operation
121

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