MC68HC705P9CDW FREESCALE [Freescale Semiconductor, Inc], MC68HC705P9CDW Datasheet - Page 67

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MC68HC705P9CDW

Manufacturer Part Number
MC68HC705P9CDW
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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5.2.2 External Reset
MC68HC705P9 — Rev. 4.0
MOTOROLA
A logic zero applied to the RESET pin for one and one-half t
generates an external reset. A Schmitt trigger senses the logic level at
the RESET pin.
Notes:
ADDRESS BUS
ADDRESS BUS
Notes:
RESET Pulse Width
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
1. Internal clock, internal address bus, and internal data bus are not available externally.
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
Freescale Semiconductor, Inc.
INTERNAL
INTERNAL
INTERNAL
DATA BUS
INTERNAL
INTERNAL
INTERNAL
OSC1 PIN
DATA BUS
For More Information On This Product,
CLOCK
RESET
CLOCK
V
DD
(NOTE 1)
Go to: www.freescale.com
Characteristic
Resets and Interrupts
Figure 5-2. Power-On Reset Timing
Figure 5-3. External Reset Timing
Table 5-1. External Reset Timing
1FFE
t
RL
1FFE
1FFE
1FFE
1FFE
4064 t
1FFE
CYC
Symbol
1FFE
t
RL
NEW
PCH
1FFE
1FFF
NEW
PCL
Min
1.5
1FFE
Resets and Interrupts
NEW PC
DUMMY
Max
1FFE
NEW
PCH
Technical Data
NEW PC
CYC
CODE
OP
1FFF
NEW
PCL
Resets
Unit
t
CYC
67

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