MC68HC705V12CFN MOTOROLA [Motorola, Inc], MC68HC705V12CFN Datasheet - Page 147
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MC68HC705V12CFN
Manufacturer Part Number
MC68HC705V12CFN
Description
The Motorola microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC705V12CFN.pdf
(248 pages)
- Current page: 147 of 248
- Download datasheet (2Mb)
14.5.1.2 Performance
MC68HC705V12
MOTOROLA
—
Rev. 3.0
Alternatively, should the counter eventually reach the value 0, the digital
filter decides that the condition of the BDRxD signal is at a stable logic
level 0 and the data latch is reset, causing the filtered Rx data signal to
become a logic level 0. Furthermore, the counter is prevented from
underflowing and can be incremented only from this state.
The data latch will retain its value until the counter next reaches the
opposite end point, signifying a definite transition of the signal.
The performance of the digital filter is best described in the time domain
rather than the frequency domain.
If the signal on the BDRxD signal transitions, then there will be a delay
before that transition appears at the filtered Rx data output signal. This
delay will be between 15 and 16 clock periods, depending on where the
transition occurs with respect to the sampling points. This filter delay
must be taken into account when performing message arbitration.
For example, if the frequency of the MUX interface clock (f
1.0486 MHz, then the period (t
delay in the absence of noise will be 15.259 s.
The effect of random noise on the BDRxD signal depends on the
characteristics of the noise itself. Narrow noise pulses on the BDRxD
signal will be ignored completely if they are shorter than the filter delay.
This provides a degree of low pass filtering.
If noise occurs during a symbol transition, the detection of that transition
can be delayed by an amount equal to the length of the noise burst. This
is just a reflection of the uncertainty of where the transition is truly
occurring within the noise.
Noise pulses that are wider than the filter delay, but narrower than the
shortest allowable symbol length, will be detected by the next stage of
the BDLC’s receiver as an invalid symbol.
Noise pulses that are longer than the shortest allowable symbol length
will be detected normally as an invalid symbol or as invalid data when
the frame’s CRC is checked.
Byte Data Link Controller – Digital (BDLC–D)
BDLC
Byte Data Link Controller – Digital (BDLC–D)
) is 954 ns and the maximum filter
BDLC MUX Interface
Advance Information
BDLC
) is
147
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