MC68HC705V12CFN MOTOROLA [Motorola, Inc], MC68HC705V12CFN Datasheet - Page 152

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MC68HC705V12CFN

Manufacturer Part Number
MC68HC705V12CFN
Description
The Motorola microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
Byte Data Link Controller – Digital (BDLC–D)
Advance Information
152
ACTIVE
PASSIVE
ACTIVE
PASSIVE
Figure 14-7. J1850 VPW Symbols with Nominal Symbol Times
ACTIVE
PASSIVE
ACTIVE
PASSIVE
(F) END OF FRAME
(C) BREAK
240 s
280 s
Logic 1
A logic 1 is defined as either:
See
Byte Data Link Controller – Digital (BDLC–D)
– An active-to-passive transition followed by a passive period
– A passive-to-active transition followed by an active period
Figure
128 s in length, or
64 s in length
(G) INTER-FRAME
SEPARATION
14-7(b).
128 s
128 s
20 s
300 s
(A) LOGIC 0
(B) LOGIC 1
(D) START OF FRAME
200 s
OR
OR
IDLE > 300 s
(H) IDLE
MC68HC705V12
64 s
64 s
(E) END OF DATA
200 s
MOTOROLA
Rev. 3.0

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