MC68HC705V12CFN MOTOROLA [Motorola, Inc], MC68HC705V12CFN Datasheet - Page 65

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MC68HC705V12CFN

Manufacturer Part Number
MC68HC705V12CFN
Description
The Motorola microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
4.8 16-Bit Timer Interrupt
4.9 BDLC Interrupt
4.10 SPI Interrupt
4.11 8-Bit Timer Interrupt
MC68HC705V12
MOTOROLA
Rev. 3.0
Three different timer interrupt flags cause a 16-bit timer interrupt
whenever they are set and enabled. The interrupt flags are in the timer
status register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts will vector to the same interrupt service
routine, located at the address specified by the contents of memory
location $3FF8 and $3FF9.
The interrupt service routine is located at the address specified by the
contents of memory location $3FF6 and $3FF7.
Two different SPI interrupt flags cause an SPI interrupt whenever they
are set and enabled. The interrupt flags are in the SPI status register
(SPSR), and the enable bits are in the SPI control register (SPCR).
Either of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory location
$3FF4 and $3FF5.
This timer can create two types of interrupts.
The real-time interrupt will vector to the interrupt service routine located
at the address specified by the contents of memory location $3FF2 and
$3FF3.
A timer overflow interrupt will occur whenever the 8-bit timer rolls
over from $FF to $00 and the enable bit TOFE is set.
A real-time interrupt will occur whenever the programmed time
elapses and the enable bit RTIE is set.
Interrupts
16-Bit Timer Interrupt
Advance Information
Interrupts
65

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