MC68HC705V12CFN MOTOROLA [Motorola, Inc], MC68HC705V12CFN Datasheet - Page 68
MC68HC705V12CFN
Manufacturer Part Number
MC68HC705V12CFN
Description
The Motorola microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC705V12CFN.pdf
(248 pages)
- Current page: 68 of 248
- Download datasheet (2Mb)
Resets
5.3 External Reset (RESET)
Advance Information
68
RESET
ADDRESS
ADDRESS
STOPEN
IRQ
DATA
OSC
V
V
DD
DD
NOTE:
(PULSE WIDTH = 3 x t
POWER-ON RESET
ILLEGAL ADDRESS
COP WATCHDOG
DISABLED STOP
LOW-VOLTAGE
INSTRUCTION
RESET (LVR)
(ILADDR)
(COPR)
The RESET pin is the only external source of a reset. This pin is
connected to a Schmitt trigger input gate to provide an upper and lower
threshold voltage separated by a minimum amount of hysteresis. This
external reset occurs whenever the RESET pin is pulled below the lower
threshold and remains in reset until the RESET pin rises above the
upper threshold. This active low input will generate the RST signal and
reset the CPU and peripherals.
Activation of the RST signal is generally referred to as reset of the
device, unless otherwise specified.
The RESET pin can also act as an open drain output. It will be pulled to
a low state by an internal pulldown that is activated by any reset source.
This reset pulldown device will be asserted only for three to four cycles
of the internal clock, f
(POR)
Figure 5-1. Reset Block Diagram
CYC
)
Resets
OP
PH2
, or as long as an internal reset source is
ONE-SHOT
CLOCKED
PH2
D
D
LATCH
LATCH
R
S
MC68HC705V12
RST
CPU
PERIPHERALS
TO OTHER
MOTOROLA
SELECT
TO IRQ
LOGIC
MODE
—
Rev. 3.0
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