MC68HC705V12CFN MOTOROLA [Motorola, Inc], MC68HC705V12CFN Datasheet - Page 61

• Manufacturer Part Number: MC68HC705V12CFN
• Description: The Motorola microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC705V12
MOTOROLA
—
Rev. 3.0
through a mask option or an MOR bit. If the edge-sensitive interrupt
option is selected for the IRQ pin, only the IRQ latch output can activate
an IRQF flag which creates an interrupt request to the CPU to generate
the external interrupt sequence.
When edge sensitivity is selected for the IRQ interrupt, it is sensitive to
these cases:
If the LEVEL select bit in the MOR is set, the active low state of the IRQ
pin can also activate an IRQF flag which creates an IRQ request to the
CPU to generate the IRQ interrupt sequence.
When edge and level sensitivity are selected for the IRQ interrupt, it is
sensitive to these cases:
The IRQE enable bit controls whether an active IRQF flag (IRQ pin
interrupt) can generate an IRQ interrupt sequence. The IPCE enable bit
controls whether an active IPCF flag (port C interrupt) can generate an
IRQ interrupt sequence. The IRQ interrupt is serviced by the interrupt
service routine located at the address specified by the contents of
$3FFA and $3FFB.
The IRQF latch is cleared automatically by entering the interrupt service
routine to maintain compatibility with existing M6805 interrupt servicing
protocol. To allow the user to identify the source of the interrupt, the port
interrupt flag (IPCF) is not cleared automatically. This flag must be
cleared within the interrupt handler prior to exit to prevent repeated
re-entry. This is achieved by writing a logic 1 to the IRQA (IRQ
acknowledge) bit, which will clear all pending IRQ interrupts, including a
pending IRQ pin interrupt.
The interrupt request flag (IPCF) is read only and cannot be cleared by
writing to it. The acknowledge flag always reads as a logic 0. Together,
1. Falling edge on the IRQ pin
2. Falling edge on any port C pin with IRQ enabled
1. Low level on the IRQ pin
2. Falling edge on the IRQ pin
3. Falling edge on any port C pin with IRQ enabled
Interrupts
External Interrupt (IRQ)
Advance Information
Interrupts
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