PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 15

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

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Semiconductor Group
PCI Configuration Space: Status/Command Register . . . . . . . . . . . . .224
Status and Command register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . .225
DSCC4 Global Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .228
GCMDR: Global Command Register . . . . . . . . . . . . . . . . . . . . . . . . . .232
GSTAR: Global Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
GMODE: Global Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
IQLENR1: Interrupt Queue Length Register 1 . . . . . . . . . . . . . . . . . . .247
IQLENR2: Interrupt Queue Length Register 2 . . . . . . . . . . . . . . . . . . .249
IQSCCiRXBAR:
Interrupt Queue SCCi Receiver Base Address Register (i=0...3) . . . .251
IQSCCiTXBAR:
Interrupt Queue SCCi Receiver Base Address Register (i=0...3) . . . .252
IQCFGBAR:
Interrupt Queue Configuration Base Address Register . . . . . . . . . . . .253
IQPBAR:
Interrupt Queue Peripheral Base Address Register. . . . . . . . . . . . . . .254
FIFOCR1: FIFO Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .255
FIFOCR2: FIFO Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .256
FIFOCR3: FIFO Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . .258
FIFOCR4: FIFO Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . .260
CHiCFG: Channel i Configuration Register (i=3...0) . . . . . . . . . . . . . .262
CHiBRDA:
Channel i Base Receive Descriptor Address Register (i=3...0) . . . . . .264
CHiBTDA:
Channel i Base Transmit Descriptor Address Register (i=3...0) . . . . .265
CHiFRDA: Channel i First (Current)
Receive Descriptor Address Register (i=3...0). . . . . . . . . . . . . . . . . . .266
CHiFTDA: Channel i First (Current)
Transmit Descriptor Address Register (i=3...0) . . . . . . . . . . . . . . . . . .267
CHiLRDA:
Channel i Last Receive Descriptor Address Register (i=3...0). . . . . . .268
CHiLTDA:
Channel i Last Transmit Descriptor Address Register (i=3...0) . . . . . .270
SCC Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273
CMDR: Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
STAR: Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
CCR0: Channel Configuration Register 0 . . . . . . . . . . . . . . . . . . . . . .283
CCR1: Channel Configuration Register 1 . . . . . . . . . . . . . . . . . . . . . .288
CCR2: Channel Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . .296
ACCM: PPP ASYNC Control Character Map . . . . . . . . . . . . . . . . . . .306
UDAC: User Defined PPP ASYNC Control Character Map . . . . . . . . .308
TTSA: Transmit Time Slot Assignment Register . . . . . . . . . . . . . . . . .310
RTSA: Receive Time Slot Assignment Register . . . . . . . . . . . . . . . . .312
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Data Sheet 09.98
PEB 20534