PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 76

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Semiconductor Group
5.1.2.3
This mode is selected by setting bit CMODE=’0’ in register GMODE (See “GMODE:
Global Mode Register” on page 241.).
The DMA controller operates on linked lists with pointer information stored in the DSCC4
internal configuration section.
The software starts DMAC operation by writing the action request bit ’AR’ in the Global
Command Register (GMCDR). On this command the DSCC4 first checks the ’IADC’ bit
of the GCMDR register. Depending on the value of GCMDR.IADC all channels are
initialized (IADC=’1’) or single channels are initialized/reset. In the latter case (IADC=’0’)
the DMAC checks all channel specific Configuration registers CHiCFG for initialization
command bits (’IDR’, ’IDT’). Setting all ’IDR’ and ’IDT’ commands in registers CHiCFG
is equal to setting ’IADC’ in register GCMDR.
Each DMA channel which is triggered for initialization by one of the above mentioned
commands fetches the Base Transmit/Receive Descriptor Address (BTDA/BRDA) from
its CHiBTDA/ChiBRDA register. The DMA channel continues reading the Tx/Rx
descriptors from the shared memory which in turn point to the associated data buffer and
the next descriptor address.
The external memory associated to a DMA channel is organized as a chained list of
buffers (typically 256 bytes) set up by an external host. Each chained list is composed of
descriptors and data sections. The descriptor contains the pointer to the next descriptor,
the start address of the data buffer and the size of a data section. In transmit direction
the data pointer is a byte address. The descriptor also includes control information like
frame end (frame end for HDLC modes, block end indication for ASYNC and extended
transparent mode), transmission hold and host initiated interrupt.
Transmit:
• In transmit direction the DMA controller reads a transmit descriptor, calculates the
data address and fills the DSCC4 central transmit FIFO. When the data transfer of the
specified section is completed, the DMA controller marks the buffer as “completed”
and branches off to the next transmit descriptor. If a frame end (FE) is indicated in the
buffer descriptor (HDLC and block oriented protocol modes), a frame end indication is
forwarded to the serial channel after the data has been transferred, and the frame will
be closed correctly by the SCC. A maskable interrupt status may be generated at the
completion of transmission to be stored in the interrupt queue by the interrupt
controller. Transmission of another frame can begin immediately.
However, if the current transmit buffer descriptor has its “HOLD” bit set, the DMA
channel does not branch off to the next descriptor. If no frame end was encountered
in the current descriptor, an active “HOLD” bit causes a transmit FIFO underrun to
occur, and a frame to be aborted by the serial channel.
Furthermore an error interrupt is generated anytime a transmit channel detects the
HOLD condition without a frame end indication asserted.
Once, the DSCC4 has sensed the HOLD=’1’ condition in transmit direction, the data
DMAC Operation Using Hold-Bit Control Mechanism
76
DMA Controller and Central FIFOs
Data Sheet 09.98
PEB 20534