PEB20534H-10 SIEMENS [Siemens Semiconductor Group], PEB20534H-10 Datasheet - Page 215

• Manufacturer Part Number: PEB20534H-10
• Description: DMA Supported Serial Communication Controller with 4 Channels DSCC4
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Table 37
Register
GMODE
IQLENR1
IQLENR2
IQSCC1RXBAR <=
IQSCC1TXBAR <=
IQCFGBAR
FIFOCR1
FIFOCR2
FIFOCR3
FIFOCR4
Semiconductor Group
Register Initialization for HDLC Transparent Mode 0, Test Loop
Access
<=
<=
<=
<= (write)
=> (read)
<=
<=
<=
<=
<=
Value
0000 0000
0000 0000
0000 0000
0000 2000
0000 4000
0000 6000
07C0 0000
0040 0000
0000 0000
0000 0000
215
RESET Value:
RESET Value:
Meaning
RESET Value:
- DMAC is controlled by HOLD bit
- Little Endian
- Default Priority Scheme
- MFP configured as LBI (not needed in
this example)
RESET Value:
Size of ring buffers: 32 entries
RESET Value:
Size of ring buffers: 32 entries
IQ Base Address for SCC1,RX
IQ Base Address for SCC1,TX
IQ Base Address for CFG
max. possible buffer of TFIFO reserved
for SCC1: 124 32-bit words
Watermark of TFIFO (SCC1 portion) is
set to 2 (example).
(As soon as less than two DWORDs are
in the central TFIFO buffer, the TFIFO
requests for more data.)
Watermark of RFIFO is set to one.
(As soon as one 32-bit word is stored in
the RFIFO, the RFIFO requests for data
transfer to shared memory.
Watermark of TFIFO forward threshold
(SCC1 portion) is set to one.
(As soon as at least one 32-bit word is in
the central TFIFO, the TFIFO transfers
data to SCC1 transmit FIFO.)
Reset and Initialization Procedure
Data Sheet 09.98
PEB 20534