PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 160

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2682/2685/4682/4685
13.2
Timer2 also can generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match)
provides the input for the 4-bit output counter/
postscaler. This counter generates the TMR2 match
interrupt flag which is latched in TMR2IF (PIR1<1>).
The interrupt is enabled by setting the TMR2 Match
Interrupt Enable bit, TMR2IE (PIE1<1>).
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).
FIGURE 13-1:
TABLE 13-1:
DS39761B-page 158
INTCON GIE/GIEH PEIE/GIEL
PIR1
PIE1
IPR1
TMR2
T2CON
PR2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1:
Name
T2OUTPS3:T2OUTPS0
T2CKPS1:T2CKPS0
F
OSC
Timer2 Interrupt
/4
Timer2 Register
Timer2 Period Register
PSPIF
PSPIE
PSPIP
These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear.
Bit 7
—
(1)
(1)
(1)
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
TIMER2 BLOCK DIAGRAM
ADIE
ADIP
Internal Data Bus
ADIF
Bit 6
1:1, 1:4, 1:16
2
Prescaler
TMR0IE
RCIF
RCIE
RCIP
Bit 5
4
TMR2
INT0IE
Bit 4
TXIF
TXIE
TXIP
Preliminary
Reset
8
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
13.3
The unscaled output of TMR2 is available primarily to
the CCP1 modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 17.0
“Master Synchronous Serial Port (MSSP) Module”.
Comparator
1:1 to 1:16
Postscaler
8
TMR2/PR2
Match
TMR2 Output
TMR0IF
CCP1IE
CCP1IP
CCP1IF
Bit 2
TMR2IE
TMR2IP
TMR2IF
INT0IF
Bit 1
© 2007 Microchip Technology Inc.
PR2
8
Set TMR2IF
TMR2 Output
(to PWM or MSSP)
TMR1IE
TMR1IP
TMR1IF
RBIF
Bit 0
on page
Values
Reset
49
52
52
52
50
50
50