PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 287

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 23-11: TXBnDLC: TRANSMIT BUFFER n DATA LENGTH CODE REGISTERS [0
REGISTER 23-12: TXERRCNT: TRANSMIT ERROR COUNT REGISTER
© 2007 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-4
bit 3-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-0
TEC7
U-0
R-0
—
Unimplemented: Read as ‘0’
TXRTR: Transmit Remote Frame Transmission Request bit
1 = Transmitted message will have TXRTR bit set
0 = Transmitted message will have TXRTR bit cleared
Unimplemented: Read as ‘0’
DLC3:DLC0: Data Length Code bits
1111 = Reserved
1110 = Reserved
1101 = Reserved
1100 = Reserved
1011 = Reserved
1010 = Reserved
1001 = Reserved
1000 = Data length = 8 bytes
0111 = Data length = 7 bytes
0110 = Data length = 6 bytes
0101 = Data length = 5 bytes
0100 = Data length = 4 bytes
0011 = Data length = 3 bytes
0010 = Data length = 2 bytes
0001 = Data length = 1 bytes
0000 = Data length = 0 bytes
TEC7:TEC0: Transmit Error Counter bits
This register contains a value which is derived from the rate at which errors occur. When the error
count overflows, the bus-off state occurs. When the bus has 128 occurrences of 11 consecutive
recessive bits, the counter value is cleared.
TXRTR
R/W-x
TEC6
R-0
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
TEC5
U-0
R-0
—
PIC18F2682/2685/4682/4685
TEC4
U-0
R-0
Preliminary
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-x
DLC3
TEC3
R-0
R/W-x
DLC2
TEC2
R-0
x = Bit is unknown
x = Bit is unknown
R/W-x
DLC1
TEC1
R-0
DS39761B-page 285
≤
R/W-x
DLC0
TEC0
R-0
n
≤
bit 0
bit 0
2]