PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 37

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

FIGURE 3-1:
FIGURE 3-2:
3.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator block using the
INTOSC multiplexer; the primary clock is shut down.
When using the INTRC source, this mode provides the
best power conservation of all the Run modes, while
still executing code. It works well for user applications
which are not highly timing sensitive or do not require
high-speed clocks at all times.
If the primary clock source is the internal oscillator
block (either INTRC or INTOSC), there are no distin-
guishable
RC_RUN modes during execution. However, a clock
switch delay will occur during entry to and exit from
RC_RUN mode. Therefore, if the primary clock source
is the internal oscillator block, the use of RC_RUN
mode is not recommended.
This mode is entered by setting SCS1 to ‘1’. Although
it is ignored, it is recommended that SCS0 also be
cleared; this is to maintain software compatibility with
future devices. When the clock source is switched to
© 2007 Microchip Technology Inc.
T1OSI
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
RC_RUN MODE
Note 1: T
differences
CPU Clock
PLL Clock
Peripheral
Program
Counter
Output
T1OSI
OSC1
Clock
Q1
SCS1:SCS0 bits Changed
OST
Q2
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
PC
= 1024 T
Q3
between
Q4
OSC
Q1
; T
Q1
PLL
1
T
OST
= 2 ms (approx). These intervals are not shown to scale.
PRI_RUN
(1)
PC
2
Q2
Clock Transition
PIC18F2682/2685/4682/4685
3
T
PLL (1)
OSTS bit Set
Q3
and
Preliminary
Q4
PC + 2
n-1
the INTOSC multiplexer (see Figure 3-3), the primary
oscillator is shut down and the OSTS bit is cleared. The
IRCF bits may be modified at any time to immediately
change the clock speed.
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output) or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of
T
n
Q1
1
IOBST
Note:
Transition
2
Clock
.
n-1 n
Q2
Caution should be used when modifying a
single IRCF bit. If V
possible to select a higher clock speed
than is supported by the low V
Improper device operation may result if
the V
PC + 2
Q3
DD
/F
Q2
OSC
Q4
Q3 Q4
specifications are violated.
Q1
Q1
DD
PC + 4
Q2
PC + 4
is less than 3V, it is
Q2
DS39761B-page 35
Q3
Q3
DD
.