PIC18F2682-I/PT MICROCHIP [Microchip Technology], PIC18F2682-I/PT Datasheet - Page 258

• Manufacturer Part Number: PIC18F2682-I/PT
• Description: 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F2682/2685/4682/4685
19.7
An A/D conversion can be started by the “Special Event
Trigger” of the ECCP1 module. This requires that the
ECCP1M3:ECCP1M0 bits (ECCP1CON<3:0>) be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D acquisition
and conversion and the Timer1 (or Timer3) counter will
be reset to zero. Timer1 (or Timer3) is reset to automat-
ically repeat the A/D acquisition period with minimal
TABLE 19-2:
DS39761B-page 256
INTCON
IPR1
PIR1
PIE1
IPR2
PIR2
PIE2
ADRESH A/D Result Register High Byte
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
TRISE
LATE
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
Note 1:
Name
(4)
2:
3:
4:
(4)
(4)
Use of the ECCP1 Trigger
These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear.
These pins may be configured as port pins depending on the oscillator mode selected.
RE3 port bit is available only as an input pin when the MCLRE Configuration bit is ‘0’.
These registers are not implemented on PIC18F2682/2685 devices.
PORTB Data Direction Register
LATB Data Output Register
TRISA7
GIE/GIEH PEIE/GIEL TMR0IE
A/D Result Register Low Byte
PSPIP
PSPIF
PSPIE
OSCFIP
OSCFIE
OSCFIF
RA7
ADFM
Bit 7
RB7
IBF
—
—
—
—
REGISTERS ASSOCIATED WITH A/D OPERATION
(2)
(1)
(1)
(1)
(2)
TRISA6
CMIP
CMIF
CMIE
RA6
ADIP
ADIF
ADIE
Bit 6
RB6
OBF
—
—
—
—
—
(2)
(1)
(1)
(1)
(2)
PORTA Data Direction Register
VCFG1
ACQT2
CHS3
RCIP
RCIF
RCIE
IBOV
Bit 5
RA5
RB5
—
—
—
—
—
PSPMODE
VCFG0
ACQT1
INT0IE
CHS2
EEIP
EEIE
Bit 4
TXIP
TXIF
TXIE
EEIF
RA4
RB4
Preliminary
—
—
PCFG3
ACQT0
SSPIP
SSPIF
SSPIE
BCLIP
BCLIE
RE3
BCLIF
CHS1
RBIE
Bit 3
RA3
RB3
software overhead (moving ADRESH/ADRESL to the
desired location). The appropriate analog input
channel must be selected and the minimum acquisition
period is either timed by the user, or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“Special Event Trigger” will be ignored by the A/D
module, but will still reset the Timer1 (or Timer3)
counter.
—
—
ACQ
(3)
time selected before the “Special Event Trigger”
LATE Data Output Register
TMR0IF
CCP1IP
CCP1IF
CCP1IE
HLVDIP
HLVDIF
HLVDIE
TRISE2
PCFG2
ADCS2
RE2
CHS0
Bit 2
RA2
RB2
(1)
GO/DONE
TMR2IP
TMR2IE
TMR3IP ECCP1IP
TMR3IE ECCP1IE
TMR2IF
TMR3IF
TRISE1
PCFG1
ADCS1
INT0IF
RE1
Bit 1
RA1
RB1
© 2007 Microchip Technology Inc.
(1)
ECCP1IF
TMR1IP
TMR1IE
TMR1IF
TRISE0
PCFG0
ADCS0
ADON
RE0
Bit 0
RBIF
RA0
RB0
(1)
(1)
(1)
(1)
on page
Values
Reset
49
52
52
52
51
52
52
50
50
50
50
51
52
52
52
52
52
52
52
52