SAB80C517-M16 SIEMENS [Siemens Semiconductor Group], SAB80C517-M16 Datasheet - Page 115

• Manufacturer Part Number: SAB80C517-M16
• Description: 8-Bit CMOS Single-Chip Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

On-Chip Peripheral Components
When using the CRC or CC4 register, you can select whether an interrupt should be generated
when the compare signal goes active or inactive, depending on the status of bits I3FR or I2FR in
T2CON, respectively.
Initializing the interrupt to be negative transition triggered is advisive in the above case. Then the
compare signal is already inactive and any write access to the port latch just changes the contents
of the "shadow-latch".
Please note that for CC registers 1 to 3 an interrupt is always requested when the compare signal
goes active.
The second configuration which should be noted is when compare functions are combined with
negative transition activated interrupts. lf the port latch of port P1.0 or P.1.4 contains a 1, the
interrupt request flags IEX3 or IEX2 will immediately be set after enabling the compare mode for the
CRC or CC4 register. The reason is that first the external interrupt input is controlled by the pin’s
level. When the compare option is enabled the interrupt logic input is switched to the internal
compare signal, which carries a low level when no true comparison is detected. So the interrupt
logic sees a 1-to-0 edge and sets the interrupt request flag.
An unintentional generation of an interrupt during compare initialization can be prevented if the
request flag is cleared by software after the compare is activated and before the external interrupt
is enabled.
7.5.5.2 Compare Function of Registers CM0 to CM7
The CCU of the SAB 80C517 contains another set of eight compare registers, an additional timer
(the compare timer) and some control SFR in the CCU which have not been described yet. These
compare registers and the compare timer are mainly dedicated to PWM applications.
The additional compare registers CM0 to CM7, however, are not permanently assigned to the
compare timer, each register may individually be configured to work either with timer 2 or the
compare timer as shown in table 7-10 on page 133.
The flexible assignment of the CMx registers allows an independent use of two time bases where
by different application requirements can be met. Any CMx register connected to the compare timer
automatically works in compare mode 0 e.g. to provide fast PWM with low CPU intervention.
Together with timer 2, CMx registers operate in compare mode 1; the latter configuration, which is
described in the next section, allows the CPU to control the compare output transitions directly.
The assignment of the eight registers CM0 to CM7 to either timer 2 or to the compare timer is done
by an 8-channel 2:1 multiplexer (shown in the general block diagram in figure 7-33). The
multiplexer can be programmed by the corresponding bits in special function register CMSEL (see
figure 7-48). The compare function itself can individually be enabled in the SFR CMEN (see
figure 7-49).
Note however that these register are not bit-addressable, which means that the value of single bits
can only be changed by AND-ing or OR-ing the register with a certain mask.
Semiconductor Group
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