SAB80C517-M16 SIEMENS [Siemens Semiconductor Group], SAB80C517-M16 Datasheet - Page 128
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SAB80C517-M16
Manufacturer Part Number
SAB80C517-M16
Description
8-Bit CMOS Single-Chip Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.SAB80C517-M16.pdf
(323 pages)
- Current page: 128 of 323
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Write Sequence
The first and the last write operation in phase one are fixed for every calculation of the MDU. All
write operations inbetween determine the type of MDU calculation.
Read Sequence
There is no restriction on the time within which a calculation must be completed. The CPU is allowed
to continue the program simultaneously to phase 2 and to fetch the result bytes at any time.
lf the user’s program takes care that interrupting a calculation is not possible, monitoring of the
calculation process is probably not needed. In this case, only the write sequence must be observed.
Any new write access to MD0 starts a new calculation, no matter whether the read-out of the former
result has been completed or not.
7.6.3
Register ARCON controls an up to 32-bit wide normalize and shift operation in registers MD0 to
MD3. lt also contains the overflow flag and the error flag which are described in the next two
sections. Figure 7-56 illustrates special function register ARCON.
Write Sequence
Semiconductor Group
– A write-to-MD0 is the first transfer to be done in any case. This write resets the MDU and
– The next two or three write operations select the calculation type (32bit/16bit, 16bit/16bit,
– Any read-out of the MDx registers should begin with MD0
– The last read from MD5 (division) or MD3 (multiplication) determines the end of a whole
– A write-to-MD0 is also the first transfer to be done for normalize and shift. This write resets
– To start a shift or normalize operation the last write must access register ARCON.
triggers the error flag mechanism (see below).
16bit x 16bit)
The last write-to-MD5 finally starts the selected MUL/DIV operation
calculation and releases the error flag mechanism.
the MDU and triggers the error flag mechanism (see below).
Normalize and Shift
129
On-Chip Peripheral Components
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