SAB80C517-M16 SIEMENS [Siemens Semiconductor Group], SAB80C517-M16 Datasheet - Page 157

• Manufacturer Part Number: SAB80C517-M16
• Description: 8-Bit CMOS Single-Chip Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Figure 8-5
Special Function Register TCON (Address 88 H )
Bit
IT0
IE0
IT1
IE1
TF0
TF1
The A/D converter interrupt is generated by IADC in register IRCON (see figure 8-7). lt is set
some cycles before the result is available. That is, if an interrupt is generated, in any case the
converted result in ADDAT is valid on the first instruction of the interrupt service routine (with
respect to the minimal interrupt response time). lf continuous conversions are established, IADC is
set once during each conversion. lf an A/D converter interrupt is generated, flag IADC will have to
be cleared by software.
The external interrupt 2 (INT2/CC4) can be either positive or negative transition-activated
depending on bit I2FR in register T2CON (see figure 8-6). The flag that actually generates this
interrupt is bit IEX2 in register IRCON. In addition, this flag will be set if a compare event occurs at
the corresponding output pin P1.4/INT2/CC4, regardless of the compare mode established and the
transition at the respective pin. lf an interrupt 2 is generated, flag IEX2 is cleared by hardware when
the service routine is vectored too.
Semiconductor Group
88 H
8F H
TF1
Function
Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low-
level triggered external interrupts.
Interrupt 0 edge flag. Set by hardware when external interrupt edge is detected.
Cleared when interrupt is initiated.
Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low-
level triggered external interrupts.
Interrupt 1 edge flag. Set by hardware when external interrupt edge is detected.
Cleared when interrupt is initiated.
Timer 0 overflow flag. Set by hardware on timer/counter overflow.
Cleared by hardware when interrupt is initiated.
Timer 1 overflow flag. Set by hardware on timer/counter overflow.
Cleared by hardware when interrupt is initiated.
These bits are not used for interrupt control.
8E H
TR1
8D H
TF0
8C H
TR0
158
8B H
IE1
8A H
IT1
89 H
IE0
Interrupt System
88 H
IT0
TCON