SAB80C517-M16 SIEMENS [Siemens Semiconductor Group], SAB80C517-M16 Datasheet - Page 156

• Manufacturer Part Number: SAB80C517-M16
• Description: 8-Bit CMOS Single-Chip Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Figure 8-4
Special Function Register IEN2 (Address 09A H )
Bit
ES1
ECT
In the following the interrupt sources are discussed individually.
The external interrupts 0 and 1 (INT0 and INT1) can each be either level-activated or negative
transition-activated, depending on bits IT0 and IT1 in register TCON (see figure 8-5). The flags that
actually generate these interrupts are bits IE0 and lE1 in TCON. When an external interrupt is
generated, the flag that generated this interrupt is cleared by the hardware when the service routine
is vectored to, but only if the interrupt was transition-activated. lf the interrupt was level-activated,
then the requesting external source directly controls the request flag, rather than the on-chip
hardware.
The timer 0 and timer 1 interrupts are generated by TF0 and TF1 in register TCON, which are set
by a rollover in their respective timer/counter registers (exception see section 7.3.4 for timer 0 in
mode 3). When a timer interrupt is generated, the flag that generated it is cleared by the on-chip
hardware when the service routine is vectored too.
The two interrupts of the serial interfaces are generated by the request flags RI0 and TI0 (in
register S0CON) or Rl1 and Tl1 (in register S1CON), respectively. Figures 7-7 and 7-12 show
SFR’s S0CON and S1CON. That is, the two request flags of each serial interface are logically OR-
ed together. Neither of these flags is cleared by hardware when the service routine is vectored too.
In fact, the service routine of each interface will normally have to determine whether it was the
receive interrupt flag or the transmission interrupt flag that generated the interrupt, and the bit will
have to be cleared by software.
The timer 2 interrupt is generated by the logical OR of bit TF2 in register T2CON and bit EXF2 in
register IRCON. Figures 8-6 and 8-7 show SFR’s T2CON and IRCON. Neither of these flags is
cleared by hardware when the service routine is vectored too. In fact, the service routine may have
to determine whether it was TF2 or EXF2 that generated the interrupt, and the bit will have to be
cleared by software.
Semiconductor Group
09A H
Function
Enable serial interrupt of interface 1. Enables or disables the interrupt of serial
interface 1. If ES1 = 0, the interrupt is disabled.
Enable compare timer interrupt. Enables or disables the interrupt at compare
timer overflow. If ECT = 0, the interrupt is disabled.
–
–
–
–
157
ECT
–
–
Interrupt System
ES1
IEN2