LPC47S457-NC SMSC [SMSC Corporation], LPC47S457-NC Datasheet - Page 183

• Manufacturer Part Number: LPC47S457-NC
• Description: Advanced I/O with X-Bus Interface
• Manufacturer: SMSC [SMSC Corporation]

SMSC LPC47S45x
WDT_CTRL
Default = 0x00
on VCC POR and
VTR POR
Default = 0000000xb
on PCI Reset
Note: Bit[0] is not
cleared by PCI Reset
FAN
Default = 0x00
Fan Control
Default = 0x10
on VTR POR
on VTR POR
NAME
REG OFFSET
Write-Only
Bit[2] is
(R/W)
(R/W)
(R/W)
(hex)
55
56
58
DATASHEET
Watch-dog timer Control
Bit[0] Watch-dog Status Bit, R/W
=1
=0
Bit[1] Reserved
Bit[2] Force Timeout, W
=1
Bit[3] P20 Force Timeout Enable, R/W
= 1
to force the WD timeout event. A WD timeout event may still be
forced by setting the Force Timeout Bit, bit 2.
= 0
Note: The P20 signal will remain high for a minimum of 1us and
can remain high indefinitely. Therefore, when P20 forced timeouts
are enabled, a self-clearing edge-detect circuit is used to generate
a signal which is ORed with the signal generated by the Force
Timeout Bit.
Bit[7:4] Reserved. Set to 0
FAN Register
Bit[0] Fan Control
Bit[6:1] Duty Cycle Control
Control the duty cycle of the FAN pin
Bit[7] Fan Clock Select
This bit is used with the Fan Clock Source Select and the Fan
Clock Multiplier bits in the Fan Control register (0x58) to determine
the fan speed F
page 124 in “Fan Speed Control and Monitoring” section.
The fan speed may be doubled through bit 2 of Fan Control
Register at 0x58.
Fan Control Register
Bit[0] Fan Clock Source Select
This bit and the Fan Clock Multiplier bit is used with The Fan Clock
Select bit in the Fan register (0x56) to determine the fan speed
F
Speed Control and Monitoring” section.
Bit[1] Reserved
Bit[2] Fan Clock Multiplier
and bit 7 of the Fan register
Bit[3] Reserved
Bit[5:4] FAN Count Divisor.
Clock scalar for adjusting the tachometer count. Default = 2.
Bit[7:6] Reserved
OUT
. See Different Modes for Fan in Table 61 on page 124 in “Fan
Page 183 of 259
WD timeout occurred
WD timer counting
Forces WD timeout event; this bit is self-clearing
Allows rising edge of P20, from the Keyboard Controller,
P20 activity does not generate the WD timeout event.
1=FAN pin is high
0=bits[6:1] control the duty cycle of the
FAN pin.
000000 = pin is low
100000 = 50% duty cycle
111111 = pin is high for 63, low for 1
0=No multiplier used
1=Double the fan speed selected by bit 0 of this register
00: divisor = 1
01: divisor = 2
10: divisor = 4
11: divisor = 8
OUT
. See Different Modes for Fan in Table 61 on
DESCRIPTION
Rev. 06-01-06